Home | History | Annotate | Download | only in ARM

Lines Matching refs:Ins

1274                                    const SmallVectorImpl<ISD::InputArg> &Ins,
1283 CCInfo.AnalyzeCallResult(Ins,
1402 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1421 Outs, OutVals, Ins, DAG);
1513 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1780 if (!Ins.empty())
1785 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1922 const SmallVectorImpl<ISD::InputArg> &Ins,
1967 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1972 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2859 &Ins,
2872 CCInfo.AnalyzeFormalArguments(Ins,
2889 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2890 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2973 // Some Ins[] entries become multiple ArgLoc[] entries.
2977 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2988 Ins[VA.getValNo()].PartOffset,