Lines Matching refs:Intrinsic
2544 case Intrinsic::arm_thread_pointer: {
2548 case Intrinsic::eh_sjlj_lsda: {
2573 case Intrinsic::arm_neon_vmulls:
2574 case Intrinsic::arm_neon_vmullu: {
2575 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3802 DAG.getConstant(Intrinsic::arm_get_fpscr,
3943 // Left shifts translate directly to the vshiftu intrinsic.
3946 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3959 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3960 Intrinsic::arm_neon_vshifts :
3961 Intrinsic::arm_neon_vshiftu);
5588 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5620 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5622 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5707 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5725 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5727 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5731 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5826 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
5839 // Intrinsic is defined to return 0 on unsupported platforms. Technically
7965 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
9047 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9048 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9050 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9052 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9054 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9056 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9058 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9060 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9062 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9064 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9066 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9068 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9070 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9072 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9074 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9146 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9156 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9163 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9166 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9169 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9215 // Now the vldN-lane intrinsic is dead except for its chain result.
9232 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9233 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9321 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9322 Intrinsic::arm_neon_vcvtfp2fxu;
9379 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9380 Intrinsic::arm_neon_vcvtfxu2fp;
9420 /// is positive, but for an intrinsic the value count must be negative. The
9448 case Intrinsic::arm_neon_vshifts:
9449 case Intrinsic::arm_neon_vshiftu:
9450 case Intrinsic::arm_neon_vshiftls:
9451 case Intrinsic::arm_neon_vshiftlu:
9452 case Intrinsic::arm_neon_vshiftn:
9453 case Intrinsic::arm_neon_vrshifts:
9454 case Intrinsic::arm_neon_vrshiftu:
9455 case Intrinsic::arm_neon_vrshiftn:
9456 case Intrinsic::arm_neon_vqshifts:
9457 case Intrinsic::arm_neon_vqshiftu:
9458 case Intrinsic::arm_neon_vqshiftsu:
9459 case Intrinsic::arm_neon_vqshiftns:
9460 case Intrinsic::arm_neon_vqshiftnu:
9461 case Intrinsic::arm_neon_vqshiftnsu:
9462 case Intrinsic::arm_neon_vqrshiftns:
9463 case Intrinsic::arm_neon_vqrshiftnu:
9464 case Intrinsic::arm_neon_vqrshiftnsu: {
9470 case Intrinsic::arm_neon_vshifts:
9471 case Intrinsic::arm_neon_vshiftu:
9477 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9483 case Intrinsic::arm_neon_vshiftls:
9484 case Intrinsic::arm_neon_vshiftlu:
9487 llvm_unreachable("invalid shift count for vshll intrinsic");
9489 case Intrinsic::arm_neon_vrshifts:
9490 case Intrinsic::arm_neon_vrshiftu:
9495 case Intrinsic::arm_neon_vqshifts:
9496 case Intrinsic::arm_neon_vqshiftu:
9501 case Intrinsic::arm_neon_vqshiftsu:
9504 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9506 case Intrinsic::arm_neon_vshiftn:
9507 case Intrinsic::arm_neon_vrshiftn:
9508 case Intrinsic::arm_neon_vqshiftns:
9509 case Intrinsic::arm_neon_vqshiftnu:
9510 case Intrinsic::arm_neon_vqshiftnsu:
9511 case Intrinsic::arm_neon_vqrshiftns:
9512 case Intrinsic::arm_neon_vqrshiftnu:
9513 case Intrinsic::arm_neon_vqrshiftnsu:
9518 "intrinsic");
9525 case Intrinsic::arm_neon_vshifts:
9526 case Intrinsic::arm_neon_vshiftu:
9529 case Intrinsic::arm_neon_vshiftls:
9530 case Intrinsic::arm_neon_vshiftlu:
9534 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
9537 case Intrinsic::arm_neon_vshiftn:
9539 case Intrinsic::arm_neon_vrshifts:
9541 case Intrinsic::arm_neon_vrshiftu:
9543 case Intrinsic::arm_neon_vrshiftn:
9545 case Intrinsic::arm_neon_vqshifts:
9547 case Intrinsic::arm_neon_vqshiftu:
9549 case Intrinsic::arm_neon_vqshiftsu:
9551 case Intrinsic::arm_neon_vqshiftns:
9553 case Intrinsic::arm_neon_vqshiftnu:
9555 case Intrinsic::arm_neon_vqshiftnsu:
9557 case Intrinsic::arm_neon_vqrshiftns:
9559 case Intrinsic::arm_neon_vqrshiftnu:
9561 case Intrinsic::arm_neon_vqrshiftnsu:
9569 case Intrinsic::arm_neon_vshiftins: {
9579 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9587 case Intrinsic::arm_neon_vqrshifts:
9588 case Intrinsic::arm_neon_vqrshiftu:
9875 case Intrinsic::arm_neon_vld1:
9876 case Intrinsic::arm_neon_vld2:
9877 case Intrinsic::arm_neon_vld3:
9878 case Intrinsic::arm_neon_vld4:
9879 case Intrinsic::arm_neon_vld2lane:
9880 case Intrinsic::arm_neon_vld3lane:
9881 case Intrinsic::arm_neon_vld4lane:
9882 case Intrinsic::arm_neon_vst1:
9883 case Intrinsic::arm_neon_vst2:
9884 case Intrinsic::arm_neon_vst3:
9885 case Intrinsic::arm_neon_vst4:
9886 case Intrinsic::arm_neon_vst2lane:
9887 case Intrinsic::arm_neon_vst3lane:
9888 case Intrinsic::arm_neon_vst4lane:
10827 /// specified in the intrinsic calls.
10830 unsigned Intrinsic) const {
10831 switch (Intrinsic) {
10832 case Intrinsic::arm_neon_vld1:
10833 case Intrinsic::arm_neon_vld2:
10834 case Intrinsic::arm_neon_vld3:
10835 case Intrinsic::arm_neon_vld4:
10836 case Intrinsic::arm_neon_vld2lane:
10837 case Intrinsic::arm_neon_vld3lane:
10838 case Intrinsic::arm_neon_vld4lane: {
10852 case Intrinsic::arm_neon_vst1:
10853 case Intrinsic::arm_neon_vst2:
10854 case Intrinsic::arm_neon_vst3:
10855 case Intrinsic::arm_neon_vst4:
10856 case Intrinsic::arm_neon_vst2lane:
10857 case Intrinsic::arm_neon_vst3lane:
10858 case Intrinsic::arm_neon_vst4lane: {
10878 case Intrinsic::arm_ldrex: {
10890 case Intrinsic::arm_strex: {
10902 case Intrinsic::arm_strexd: {
10913 case Intrinsic::arm_ldrexd: {
