Lines Matching refs:MIB
6048 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6050 MIB.addImm(0);
6051 AddDefaultPred(MIB);
6064 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
6066 MIB.addImm(0);
6067 AddDefaultPred(MIB);
6154 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6156 MIB.addImm(0);
6157 AddDefaultPred(MIB);
6168 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6170 MIB.addImm(0);
6171 AddDefaultPred(MIB);
6267 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6269 MIB.addImm(0);
6270 AddDefaultPred(MIB);
6286 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6288 MIB.addImm(0);
6289 AddDefaultPred(MIB);
6696 MachineInstrBuilder MIB;
6697 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6704 MIB.addRegMask(RI.getNoPreservedMask());
6969 MachineInstrBuilder MIB(*MF, &*II);
6982 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7259 MachineInstrBuilder MIB = BuildMI(BB, dl,
7261 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7262 MIB->getOperand(5).setReg(ARM::CPSR);
7263 MIB->getOperand(5).setIsDef(true);
7368 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7370 MIB.addOperand(MI->getOperand(i));
