Lines Matching refs:MVT
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
108 if (ElemTy == MVT::i32) {
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
431 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
433 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
436 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
438 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
443 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
444 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
446 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
447 setTruncStoreAction((MVT::SimpleValueType)VT,
448 (MVT::SimpleValueType)InnerVT, Expand);
449 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
450 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
451 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
454 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
457 addDRTypeForNEON(MVT::v2f32);
458 addDRTypeForNEON(MVT::v8i8);
459 addDRTypeForNEON(MVT::v4i16);
460 addDRTypeForNEON(MVT::v2i32);
461 addDRTypeForNEON(MVT::v1i64);
463 addQRTypeForNEON(MVT::v4f32);
464 addQRTypeForNEON(MVT::v2f64);
465 addQRTypeForNEON(MVT::v16i8);
466 addQRTypeForNEON(MVT::v8i16);
467 addQRTypeForNEON(MVT::v4i32);
468 addQRTypeForNEON(MVT::v2i64);
474 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
475 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
476 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
479 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
480 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
484 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
487 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
489 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
490 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
491 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
492 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
493 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
494 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
495 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
496 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
497 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
498 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
499 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
500 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
502 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
503 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
504 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
505 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
506 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
507 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
509 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
510 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
511 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
512 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
513 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
515 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
516 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
517 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
518 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
519 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
520 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
521 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
522 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
523 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
526 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
527 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
528 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
529 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
530 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
531 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
532 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
533 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
534 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
535 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
536 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
537 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
538 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
539 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
540 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
543 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
545 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
546 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
547 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
549 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
550 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
551 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
552 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
553 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
554 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
560 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
561 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
562 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
564 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
565 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
568 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
569 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
570 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
571 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
572 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
573 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
574 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
575 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
580 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
581 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
582 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
583 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
587 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
588 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
610 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
611 MVT::v4i16, MVT::v2i16,
612 MVT::v2i32};
628 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
631 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
637 setIndexedLoadAction(im, MVT::i1, Legal);
638 setIndexedLoadAction(im, MVT::i8, Legal);
639 setIndexedLoadAction(im, MVT::i16, Legal);
640 setIndexedLoadAction(im, MVT::i32, Legal);
641 setIndexedStoreAction(im, MVT::i1, Legal);
642 setIndexedStoreAction(im, MVT::i8, Legal);
643 setIndexedStoreAction(im, MVT::i16, Legal);
644 setIndexedStoreAction(im, MVT::i32, Legal);
649 setOperationAction(ISD::MUL, MVT::i64, Expand);
650 setOperationAction(ISD::MULHU, MVT::i32, Expand);
652 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
653 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
657 setOperationAction(ISD::MULHS, MVT::i32, Expand);
659 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
660 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
661 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
662 setOperationAction(ISD::SRL, MVT::i64, Custom);
663 setOperationAction(ISD::SRA, MVT::i64, Custom);
667 setOperationAction(ISD::ADDC, MVT::i32, Custom);
668 setOperationAction(ISD::ADDE, MVT::i32, Custom);
669 setOperationAction(ISD::SUBC, MVT::i32, Custom);
670 setOperationAction(ISD::SUBE, MVT::i32, Custom);
674 setOperationAction(ISD::ROTL, MVT::i32, Expand);
675 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
676 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
678 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
681 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
682 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
684 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
688 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
693 setOperationAction(ISD::SDIV, MVT::i32, Expand);
694 setOperationAction(ISD::UDIV, MVT::i32, Expand);
698 setOperationAction(ISD::SREM, MVT::i32, Expand);
699 setOperationAction(ISD::UREM, MVT::i32, Expand);
720 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
721 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
723 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
724 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
727 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
728 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
729 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
730 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
731 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
733 setOperationAction(ISD::TRAP, MVT::Other, Legal);
736 setOperationAction(ISD::VASTART, MVT::Other, Custom);
737 setOperationAction(ISD::VAARG, MVT::Other, Expand);
738 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
739 setOperationAction(ISD::VAEND, MVT::Other, Expand);
740 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
741 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
750 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
758 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
760 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
761 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
762 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
763 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
764 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
765 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
766 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
767 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
768 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
769 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
770 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
775 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
776 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
777 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
778 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
779 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
780 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
781 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
782 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
783 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
784 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
785 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
790 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
791 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
794 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
798 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
799 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
801 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
807 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
808 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
812 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
814 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
815 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
819 setOperationAction(ISD::SETCC, MVT::i32, Expand);
820 setOperationAction(ISD::SETCC, MVT::f32, Expand);
821 setOperationAction(ISD::SETCC, MVT::f64, Expand);
822 setOperationAction(ISD::SELECT, MVT::i32, Custom);
823 setOperationAction(ISD::SELECT, MVT::f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::f64, Custom);
825 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
826 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
827 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
829 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
830 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
831 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
832 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
833 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
836 setOperationAction(ISD::FSIN, MVT::f64, Expand);
837 setOperationAction(ISD::FSIN, MVT::f32, Expand);
838 setOperationAction(ISD::FCOS, MVT::f32, Expand);
839 setOperationAction(ISD::FCOS, MVT::f64, Expand);
840 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
841 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
842 setOperationAction(ISD::FREM, MVT::f64, Expand);
843 setOperationAction(ISD::FREM, MVT::f32, Expand);
846 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
847 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
849 setOperationAction(ISD::FPOW, MVT::f64, Expand);
850 setOperationAction(ISD::FPOW, MVT::f32, Expand);
853 setOperationAction(ISD::FMA, MVT::f64, Expand);
854 setOperationAction(ISD::FMA, MVT::f32, Expand);
861 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
862 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
863 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
864 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
868 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
869 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
922 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
931 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
932 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
941 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
942 case MVT::v4f32: case MVT::v2f64:
946 case MVT::v4i64:
950 case MVT::v8i64:
1118 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1123 if (VT == MVT::v4i64)
1125 if (VT == MVT::v8i64)
1151 if (VT == MVT::Glue || VT == MVT::Other)
1294 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1303 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1308 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1312 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1314 if (VA.getLocVT() == MVT::v2f64) {
1315 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1316 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1317 DAG.getConstant(0, MVT::i32));
1320 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1324 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1327 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1328 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1329 DAG.getConstant(1, MVT::i32));
1376 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1486 if (VA.getLocVT() == MVT::v2f64) {
1487 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1488 DAG.getConstant(0, MVT::i32));
1489 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1490 DAG.getConstant(1, MVT::i32));
1510 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1511 assert(VA.getLocVT() == MVT::i32 &&
1513 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1535 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1559 MVT::i32);
1560 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1562 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1576 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1633 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1648 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1669 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1674 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1698 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1703 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1770 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2035 if (RegVT == MVT::v2f64) {
2104 if (VA.getLocVT() == MVT::v2f64) {
2106 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2107 DAG.getConstant(0, MVT::i32));
2109 DAG.getVTList(MVT::i32, MVT::i32), Half);
2122 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2123 DAG.getConstant(1, MVT::i32));
2128 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
2149 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other,
2164 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2245 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2278 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2296 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2302 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2347 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2353 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2365 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2407 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2432 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2480 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2488 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2513 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2517 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2524 SDValue Val = DAG.getConstant(0, MVT::i32);
2526 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2533 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2534 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2561 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2568 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2593 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2594 DAG.getConstant(0, MVT::i32));
2607 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2608 DAG.getConstant(Domain, MVT::i32));
2633 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2634 MVT::i32),
2635 DAG.getConstant(isData, MVT::i32));
2667 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2676 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2681 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2684 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2812 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2825 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2898 if (VA.getLocVT() == MVT::v2f64) {
2906 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2913 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2914 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2916 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2924 if (RegVT == MVT::f32)
2926 else if (RegVT == MVT::f64)
2928 else if (RegVT == MVT::v2f64)
2930 else if (RegVT == MVT::i32)
2969 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3051 RHS = DAG.getConstant(C-1, MVT::i32);
3058 RHS = DAG.getConstant(C-1, MVT::i32);
3065 RHS = DAG.getConstant(C+1, MVT::i32);
3072 RHS = DAG.getConstant(C+1, MVT::i32);
3091 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3092 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3101 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3103 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3104 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3114 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3120 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3123 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3125 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3189 if (LHS.getValueType() == MVT::i32) {
3191 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3199 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3201 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3205 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3225 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3239 return DAG.getConstant(0, MVT::i32);
3242 return DAG.getLoad(MVT::i32, SDLoc(Op),
3253 RetVal1 = DAG.getConstant(0, MVT::i32);
3254 RetVal2 = DAG.getConstant(0, MVT::i32);
3260 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3270 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3305 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3307 if (LHS.getValueType() == MVT::f32) {
3308 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3310 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3313 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3314 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3322 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3323 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3325 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3326 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3342 if (LHS.getValueType() == MVT::i32) {
3345 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3346 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3350 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3363 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3365 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3366 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3370 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3388 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3396 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3400 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3405 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3411 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3419 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3420 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3425 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3427 if (VT != MVT::v4i16)
3430 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3451 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3452 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3459 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3460 if (VT.getVectorElementType() == MVT::f32)
3465 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3467 if (VT != MVT::v4f32)
3484 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3506 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3524 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3525 DAG.getTargetConstant(EncodedVal, MVT::i32));
3526 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3527 if (VT == MVT::f64)
3530 DAG.getConstant(32, MVT::i32));
3531 else /*if (VT == MVT::f32)*/
3532 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3533 if (SrcVT == MVT::f32) {
3534 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3535 if (VT == MVT::f64)
3538 DAG.getConstant(32, MVT::i32));
3539 } else if (VT == MVT::f32)
3540 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3541 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3542 DAG.getConstant(32, MVT::i32));
3547 MVT::i32);
3548 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3555 if (VT == MVT::f32) {
3556 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3557 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3558 DAG.getConstant(0, MVT::i32));
3560 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3567 if (SrcVT == MVT::f64)
3568 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3570 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3573 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3574 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3575 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3576 if (VT == MVT::f32) {
3577 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3578 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3579 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3580 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3584 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3587 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3588 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3589 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3602 SDValue Offset = DAG.getConstant(4, MVT::i32);
3609 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3685 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3689 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3690 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3691 DAG.getConstant(0, MVT::i32));
3692 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3693 DAG.getConstant(1, MVT::i32));
3695 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3699 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3701 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3703 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3718 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3719 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3740 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3741 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3743 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3744 DAG.getConstant(VTBits, MVT::i32));
3749 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3750 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3774 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3775 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3777 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3778 DAG.getConstant(VTBits, MVT::i32));
3783 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3784 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3801 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3803 MVT::i32));
3804 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3805 DAG.getConstant(1U << 22, MVT::i32));
3806 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3807 DAG.getConstant(22, MVT::i32));
3808 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3809 DAG.getConstant(3, MVT::i32));
3841 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
3865 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
3866 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3869 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
3871 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
3898 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
3907 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
3908 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
3911 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
3913 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
3922 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
3923 VT == MVT::v4i16 || VT == MVT::v8i16) &&
3926 if (VT.getVectorElementType() == MVT::i32)
3946 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3963 DAG.getConstant(vshiftInt, MVT::i32),
3973 if (VT != MVT::i64)
3988 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3989 DAG.getConstant(0, MVT::i32));
3990 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3991 DAG.getConstant(1, MVT::i32));
3996 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3999 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4002 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4160 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4165 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4185 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4260 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4269 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4278 assert(Op.getValueType() == MVT::f32 &&
4286 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4287 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4289 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4290 DAG.getConstant(0, MVT::i32));
4302 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4304 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4305 DAG.getConstant(0, MVT
4314 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4316 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4317 DAG.getConstant(0, MVT::i32));
4423 return VT == MVT::v8i8 && M.size() == 8;
4580 return DAG.getConstant(Val, MVT::i32);
4583 return DAG.getConstant(Val, MVT::i32);
4624 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4627 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4709 Value, DAG.getConstant(index, MVT::i32)),
4710 DAG.getConstant(index, MVT::i32));
4726 Ops.push_back(DAG.getConstant(I, MVT::i32));
4735 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4737 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4790 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
4910 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4985 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5030 if (VT.getVectorElementType() == MVT::i32 ||
5031 VT.getVectorElementType() == MVT::f32)
5034 if (VT.getVectorElementType() == MVT::i16)
5037 assert(VT.getVectorElementType() == MVT::i8);
5044 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5050 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5077 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5080 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5081 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5084 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5085 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5095 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5101 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5103 DAG.getConstant(ExtractNum, MVT::i32));
5147 DAG.getConstant(Lane, MVT::i32));
5156 DAG.getConstant(Imm, MVT::i32));
5169 DAG.getConstant(Imm, MVT::i32));
5237 MVT::i32)));
5243 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5246 if (VT == MVT::v8i8) {
5271 if (Op.getValueType() == MVT::i32 &&
5274 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5286 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5290 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5291 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5294 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5295 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5307 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5309 if (BVN->getValueType(0) != MVT::v4i32 ||
5380 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5383 case MVT::v2i8:
5384 case MVT::v2i16:
5385 return MVT::v2i32;
5386 case MVT::v4i8:
5387 return MVT::v4i16;
5456 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5458 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5466 MVT TruncVT = MVT::getIntegerVT(EltSize);
5473 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5476 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
5537 if (VT == MVT::v2i64)
5581 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5582 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5583 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5584 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5587 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5588 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5593 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5594 MVT::v4i32, X);
5595 Y = DAG.getConstant(0xb000, MVT::i32);
5596 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5597 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5598 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5600 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5601 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5611 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5612 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5613 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5614 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5619 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5620 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5621 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5622 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5624 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5629 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5630 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5631 N1 = DAG.getConstant(0x89, MVT::i32);
5632 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5633 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5634 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5637 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5638 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5644 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5652 if (VT == MVT::v8i8) {
5653 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5654 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5656 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5658 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5660 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5662 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5668 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5671 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5679 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5687 if (VT == MVT::v8i8) {
5688 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5689 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5691 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5693 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5695 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5697 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5703 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5706 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5707 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5715 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5716 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5717 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5718 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5724 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5725 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5726 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5727 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5729 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5730 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5731 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5733 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5738 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5739 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5740 N1 = DAG.getConstant(2, MVT::i32);
5741 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5742 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5743 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5746 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5747 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5753 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5786 assert (Node->getValueType(0) == MVT::i64 &&
5793 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5796 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5800 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5803 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5806 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
5808 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5811 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
5826 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
5827 DAG.getConstant(15, MVT::i32),
5828 DAG.getConstant(0, MVT::i32),
5829 DAG.getConstant(9, MVT::i32),
5830 DAG.getConstant(13, MVT::i32),
5831 DAG.getConstant(0, MVT::i32)
5835 DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
5842 Cycles32 = DAG.getConstant(0, MVT::i32);
5847 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
5848 Cycles32, DAG.getConstant(0, MVT::i32));
7813 if (CC.getValueType() != MVT::i1)
7913 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7972 MVT widenType;
7975 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7976 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7977 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8026 AddcNode->getValueType(0) == MVT::i32 &&
8030 if (AddcNode->getValueType(1) != MVT::Glue)
8050 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8113 DAG.getVTList(MVT::i32, MVT::i32),
8242 if (VT != MVT::i32)
8267 MVT::i32)));
8274 MVT::i32)),
8287 MVT::i32)));
8295 MVT::i32)));
8297 DAG.getConstant(0, MVT::i32),Res);
8305 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8425 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8454 if (VT != MVT::i32)
8481 DAG.getConstant(Val, MVT::i32),
8482 DAG.getConstant(Mask, MVT::i32));
8507 DAG.getConstant(amt, MVT::i32));
8509 DAG.getConstant(Mask, MVT::i32));
8523 DAG.getConstant(lsb, MVT::i32));
8525 DAG.getConstant(Mask2, MVT::i32));
8544 DAG.getConstant(~Mask, MVT::i32));
8606 InNode->getValueType(0) == MVT::f64 &&
8615 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8620 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8621 DAG.getConstant(4, MVT::i32));
8622 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8707 MVT StoreType = MVT::i8;
8708 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8709 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8710 MVT Tp = (MVT::SimpleValueType)tp;
8741 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
8760 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8761 DAG.getConstant(4, MVT::i32));
8768 if (StVal.getValueType() != MVT::i64 ||
8777 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8780 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8783 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8826 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8832 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8837 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8865 assert(EltVT == MVT::f32 && "Unexpected type!");
8885 if (Elt->getOperand(0).getValueType() == MVT::i32)
8899 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8917 V->getOperand(0).getValueType() == MVT::i32)
8921 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8925 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8942 if (VT.getVectorElementType() != MVT::i64 ||
8948 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8951 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9115 Tys[n++] = MVT::i32;
9116 Tys[n] = MVT::Other;
9196 Tys[n] = MVT::Other;
9312 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9313 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9325 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9326 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9327 DAG.getConstant(Log2_64(C), MVT::i32));
9363 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9364 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9376 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9383 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9384 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9566 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9584 DAG.getConstant(Cnt, MVT::i32));
9604 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9631 DAG.getConstant(Cnt, MVT::i32));
9640 DAG.getConstant(Cnt, MVT::i32));
9663 if (VT == MVT::i32 &&
9664 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9699 N->getValueType(0) != MVT::f32)
9822 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9823 DAG.getValueType(MVT::i1));
9825 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9826 DAG.getValueType(MVT::i8));
9828 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9829 DAG.getValueType(MVT::i16));
9899 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9909 case MVT::i8:
9910 case MVT::i16:
9911 case MVT::i32: {
9920 case MVT::f64:
9921 case MVT::v2f64: {
9956 (allowsUnalignedMemoryAccesses(MVT::v2f64, &Fast) && Fast))) {
9957 return MVT::v2f64;
9960 (allowsUnalignedMemoryAccesses(MVT::f64, &Fast) && Fast))) {
9961 return MVT::f64;
9967 return MVT::i32;
9969 return MVT::i16;
9972 return MVT::Other;
9986 case MVT::i1:
9987 case MVT::i8:
9988 case MVT::i16:
10018 case MVT::i1:
10019 case MVT::i8:
10022 case MVT::i16:
10026 case MVT::i32:
10048 case MVT::i1:
10049 case MVT::i8:
10050 case MVT::i16:
10051 case MVT::i32:
10056 case MVT::f32:
10057 case MVT::f64:
10089 case MVT::i1:
10090 case MVT::i8:
10091 case MVT::i32:
10094 case MVT::i16:
10097 case MVT::f32:
10098 case MVT::f64:
10116 case MVT::i1:
10117 case MVT::i8:
10118 case MVT::i16:
10119 case MVT::i32:
10125 case MVT::i64:
10130 case MVT::isVoid:
10174 case MVT::i1:
10175 case MVT::i8:
10176 case MVT::i32:
10182 case MVT::i16:
10183 case MVT::i64:
10189 case MVT::isVoid:
10238 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10253 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10536 MVT VT) const {
10551 if (VT == MVT::f32)
10559 if (VT == MVT::f32)
10567 if (VT == MVT::f32)
10757 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10758 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10759 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10760 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10818 if (VT == MVT::f32)
10820 if (VT == MVT::f64)
10842 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10868 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10881 Info.memVT = MVT::getVT(PtrTy->getElementType());
10893 Info.memVT = MVT::getVT(PtrTy->getElementType());
10904 Info.memVT = MVT::i64;
10915 Info.memVT = MVT::i64;
