Lines Matching refs:VA
1289 CCValAssign VA = RVLocs[i];
1294 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1301 if (VA.needsCustom()) {
1303 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1307 VA = RVLocs[++i]; // skip ahead to next loc
1308 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1314 if (VA.getLocVT() == MVT::v2f64) {
1319 VA = RVLocs[++i]; // skip ahead to next loc
1320 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1323 VA = RVLocs[++i]; // skip ahead to next loc
1324 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1332 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1338 switch (VA.getLocInfo()) {
1342 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1357 const CCValAssign &VA,
1359 unsigned LocMemOffset = VA.getLocMemOffset();
1370 CCValAssign &VA, CCValAssign &NextVA,
1377 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1461 CCValAssign &VA = ArgLocs[i];
1467 switch (VA.getLocInfo()) {
1471 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1474 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1477 VA.getLocVT(), Arg);
1480 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1485 if (VA.needsCustom()) {
1486 if (VA.getLocVT() == MVT::v2f64) {
1493 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1495 VA = ArgLocs[++i]; // skip ahead to next loc
1496 if (VA.isRegLoc()) {
1498 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1500 assert(VA.isMemLoc());
1503 dl, DAG, VA, Flags));
1506 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1509 } else if (VA.isRegLoc()) {
1511 assert(VA.getLocVT() == MVT::i32 &&
1517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1519 assert(VA.isMemLoc());
1552 unsigned LocMemOffset = VA.getLocMemOffset();
1568 assert(VA.isMemLoc());
1571 dl, DAG, VA, Flags));
2020 CCValAssign &VA = ArgLocs[i];
2021 EVT RegVT = VA.getLocVT();
2024 if (VA.getLocInfo() == CCValAssign::Indirect)
2026 if (VA.needsCustom()) {
2031 if (!VA.isRegLoc())
2041 } else if (!VA.isRegLoc()) {
2042 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2090 CCValAssign &VA = RVLocs[i];
2091 assert(VA.isRegLoc() && "Can only return in registers!");
2095 switch (VA.getLocInfo()) {
2099 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2103 if (VA.needsCustom()) {
2104 if (VA.getLocVT() == MVT::v2f64) {
2111 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
2113 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2114 VA = RVLocs[++i]; // skip ahead to next loc
2115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2118 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2119 VA = RVLocs[++i]; // skip ahead to next loc
2129 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2131 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2132 VA = RVLocs[++i]; // skip ahead to next loc
2133 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2136 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2141 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2653 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2666 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2888 CCValAssign &VA = ArgLocs[i];
2889 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2890 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2892 if (VA.isRegLoc()) {
2893 EVT RegVT = VA.getLocVT();
2895 if (VA.needsCustom()) {
2898 if (VA.getLocVT() == MVT::v2f64) {
2899 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2901 VA = ArgLocs[++i]; // skip ahead to next loc
2903 if (VA.isMemLoc()) {
2904 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2910 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2919 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2938 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2945 switch (VA.getLocInfo()) {
2949 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2953 DAG.getValueType(VA.getValVT()));
2954 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2958 DAG.getValueType(VA.getValVT()));
2959 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2965 } else { // VA.isRegLoc()
2968 assert(VA.isMemLoc());
2969 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2988 Ins[VA.getValNo()].PartOffset,
2989 VA.getLocMemOffset(),
2995 unsigned FIOffset = VA.getLocMemOffset() +
2997 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3002 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
