Lines Matching defs:NewOpc
776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
875 unsigned NewOpc = 0;
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
953 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
962 if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
965 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
971 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
1075 DebugLoc dl, unsigned NewOpc,
1083 TII->get(NewOpc))
1089 TII->get(NewOpc))
1135 unsigned NewOpc = (isLd)
1139 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1146 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1158 unsigned NewOpc = (isLd)
1178 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1193 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1421 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET);
1424 PrevMI->setDesc(TII->get(NewOpc));
1481 unsigned &NewOpc, unsigned &EvenReg,
1577 unsigned &NewOpc, unsigned &EvenReg,
1590 NewOpc = ARM::LDRD;
1592 NewOpc = ARM::STRD;
1594 NewOpc = ARM::t2LDRDi8;
1598 NewOpc = ARM::t2STRDi8;
1744 unsigned NewOpc = 0;
1747 if (NumMove == 2 && CanFormLdStDWord(Op0, Op1, dl, NewOpc,
1753 const MCInstrDesc &MCID = TII->get(NewOpc);
