Lines Matching defs:PredReg
95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl,
340 .addImm(Pred).addReg(PredReg).addReg(0);
351 .addImm(Pred).addReg(PredReg);
371 ARMCC::CondCodes Pred, unsigned PredReg,
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs))
448 ARMCC::CondCodes Pred, unsigned PredReg,
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
500 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
511 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
531 ARMCC::CondCodes Pred, unsigned PredReg) {
556 MyPredReg == PredReg))
564 ARMCC::CondCodes Pred, unsigned PredReg) {
589 MyPredReg == PredReg))
718 unsigned PredReg = 0;
719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
739 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
743 isMatchingDecrement(PrevMBBI, Base, Bytes, 0, Pred, PredReg)) {
758 isMatchingIncrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
761 isMatchingDecrement(NextMBBI, Base, Bytes, 0, Pred, PredReg)) {
780 .addImm(Pred).addReg(PredReg);
871 unsigned PredReg = 0;
872 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
885 if (isMatchingDecrement(PrevMBBI, Base, Bytes, Limit, Pred, PredReg)) {
889 isMatchingIncrement(PrevMBBI, Base, Bytes, Limit,Pred,PredReg)) {
905 isMatchingDecrement(NextMBBI, Base, Bytes, Limit, Pred, PredReg)) {
908 } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Limit,Pred,PredReg)) {
933 .addImm(Pred).addReg(PredReg)
943 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
948 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
955 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
967 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
973 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1079 ARMCC::CondCodes Pred, unsigned PredReg,
1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1092 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1129 unsigned PredReg = 0;
1130 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1141 .addImm(Pred).addReg(PredReg)
1148 .addImm(Pred).addReg(PredReg)
1176 Pred, PredReg, TII, isT2);
1181 Pred, PredReg, TII, isT2);
1196 Pred, PredReg, TII, isT2);
1201 Pred, PredReg, TII, isT2);
1248 unsigned PredReg = 0;
1249 ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
1283 CurrPredReg = PredReg;
1294 // No need to match PredReg.
1484 unsigned &PredReg, ARMCC::CondCodes &Pred,
1579 int &Offset, unsigned &PredReg,
1642 Pred = getInstrPredicate(Op0, PredReg);
1741 unsigned BaseReg = 0, PredReg = 0;
1749 Offset, PredReg, Pred, isT2)) {
1769 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1783 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1838 unsigned PredReg = 0;
1839 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
