Lines Matching full:opcode
94 int Offset, unsigned Base, bool BaseKill, int Opcode,
107 int Opcode,
114 int Opcode, unsigned Size,
137 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
138 switch (Opcode) {
139 default: llvm_unreachable("Unhandled opcode!");
208 AMSubMode getLoadStoreMultipleSubMode(int Opcode) {
209 switch (Opcode) {
210 default: llvm_unreachable("Unhandled opcode!");
285 int Opcode, ARMCC::CondCodes Pred,
296 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
306 // Check if this is a supported opcode before we insert instructions to
308 if (!getLoadStoreMultipleOpcode(Opcode, Mode)) return false;
317 if (isi32Load(Opcode))
345 bool isDef = (isi32Load(Opcode) || Opcode == ARM::VLDRS ||
346 Opcode == ARM::VLDRD);
347 Opcode = getLoadStoreMultipleOpcode(Opcode, Mode);
348 if (!Opcode) return false;
349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
370 int Opcode,
415 if (!MergeOps(MBB, Loc, Offset, Base, BaseKill, Opcode,
447 unsigned Base, int Opcode, unsigned Size,
451 bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
465 switch (Opcode) {
499 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges);
500 MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,
511 Base, BaseKill, Opcode, Pred, PredReg, Scratch, dl, Merges);
634 default: llvm_unreachable("Unhandled opcode!");
720 int Opcode = MI->getOpcode();
730 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(Opcode);
776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode);
814 default: llvm_unreachable("Unhandled opcode!");
839 default: llvm_unreachable("Unhandled opcode!");
854 int Opcode = MI->getOpcode();
856 bool isAM5 = (Opcode == ARM::VLDRD || Opcode == ARM::VLDRS ||
857 Opcode == ARM::VSTRD || Opcode == ARM::VSTRS);
858 bool isAM2 = (Opcode == ARM::LDRi12 || Opcode == ARM::STRi12);
859 if (isi32Load(Opcode) || isi32Store(Opcode))
865 bool isLd = isi32Load(Opcode) || Opcode == ARM::VLDRS || Opcode == ARM::VLDRD;
893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub);
912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub);
1012 int Opcode = MI->getOpcode();
1013 switch (Opcode) {
1049 int Opcode = MI->getOpcode();
1050 bool isAM3 = Opcode == ARM::LDRD || Opcode == ARM::STRD;
1054 if (Opcode == ARM::t2LDRi12 || Opcode == ARM::t2LDRi8 ||
1055 Opcode == ARM::t2STRi12 || Opcode == ARM::t2STRi8 ||
1056 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8 ||
1057 Opcode == ARM::LDRi12 || Opcode == ARM::STRi12)
1099 unsigned Opcode = MI->getOpcode();
1100 if (Opcode == ARM::LDRD || Opcode == ARM::STRD ||
1101 Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8) {
1116 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8;
1117 bool isLd = Opcode == ARM::LDRD || Opcode == ARM::t2LDRDi8;
1242 int Opcode = MBBI->getOpcode();
1260 Clobber = (isi32Load(Opcode) && Base == MBBI->getOperand(0).getReg());
1280 CurrOpc = Opcode;
1293 if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
1414 unsigned Opcode = PrevMI->getOpcode();
1415 if (Opcode == ARM::LDMIA_UPD || Opcode == ARM::LDMDA_UPD ||
1416 Opcode == ARM::LDMDB_UPD || Opcode == ARM::LDMIB_UPD ||
1417 Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
1422 assert(((isThumb2 && Opcode == ARM::t2LDMIA_UPD) ||
1423 Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
1588 unsigned Opcode = Op0->getOpcode();
1589 if (Opcode == ARM::LDRi12)
1591 else if (Opcode == ARM::STRi12)
1593 else if (Opcode == ARM::t2LDRi8 || Opcode == ARM::t2LDRi12) {
1597 } else if (Opcode == ARM::t2STRi8 || Opcode == ARM::t2STRi12) {
