Lines Matching defs:ISD
181 int ISD = TLI->InstructionOpcodeToISD(Opcode);
182 assert(ISD && "Invalid opcode");
187 { ISD::FP_ROUND, MVT::v2f64, 2 },
188 { ISD::FP_EXTEND, MVT::v2f32, 2 },
189 { ISD::FP_EXTEND, MVT::v4f32, 4 }
192 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
193 ISD == ISD::FP_EXTEND)) {
196 ISD, LT.second);
211 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
212 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
213 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
214 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
215 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
216 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
219 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
220 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
221 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
222 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
223 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
224 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
225 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
226 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
227 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
228 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
231 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
232 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
235 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
236 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
238 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
239 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
240 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
241 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
242 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
243 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
244 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
246 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
247 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
248 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
249 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
250 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
251 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
252 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
253 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
254 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
255 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
256 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
257 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
259 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
261 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
262 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
263 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
264 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
267 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
268 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
270 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
271 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
272 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
273 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
274 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
275 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
277 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
278 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
279 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
280 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
281 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
282 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
288 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
295 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
296 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
297 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
298 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
299 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
300 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
301 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
302 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
303 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
304 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
305 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
306 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
307 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
308 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
309 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
310 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
311 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
312 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
313 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
314 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
319 ISD, DstTy.getSimpleVT(),
327 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
328 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
329 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
330 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
333 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
334 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
335 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
336 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
337 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
338 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
339 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
340 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
341 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
342 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
343 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
344 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
345 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
346 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
352 ISD, DstTy.getSimpleVT(),
361 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
364 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
365 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
366 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
367 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
374 ISD, DstTy.getSimpleVT(),
399 int ISD = TLI->InstructionOpcodeToISD(Opcode);
401 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
404 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
405 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
406 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
407 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
408 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
409 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
417 ISD, SelCondTy.getSimpleVT(),
454 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
455 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
456 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
457 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
459 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
460 { ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 },
461 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
462 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
468 ISD::VECTOR_SHUFFLE, LT.second);
488 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
489 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost},
490 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
491 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
492 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
493 { ISD::UDIV, MVT::v2i32, 2 * FunctionCallDivCost},
494 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
495 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
496 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
497 { ISD::UDIV, MVT::v4i16, ReciprocalDivCost},
498 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
499 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
500 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
501 { ISD::UDIV, MVT::v8i8, ReciprocalDivCost},
502 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
503 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
505 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
506 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
507 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
508 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
509 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
510 { ISD::UDIV, MVT::v4i32, 4 * FunctionCallDivCost},
511 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
512 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
513 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
514 { ISD::UDIV, MVT::v8i16, 8 * FunctionCallDivCost},
515 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
516 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
517 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
518 { ISD::UDIV, MVT::v16i8, 16 * FunctionCallDivCost},
519 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
520 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
