Lines Matching refs:getReg
550 unsigned getReg() const {
1529 Inst.addOperand(MCOperand::CreateReg(getReg()));
1534 Inst.addOperand(MCOperand::CreateReg(getReg()));
2470 OS << "<ccout " << getReg() << ">";
2525 OS << "<register " << getReg() << ">";
2685 int SrcReg = PrevOp->getReg();
4097 ((ARMOperand*)Operands[4])->getReg() ==
4098 ((ARMOperand*)Operands[3])->getReg())
4750 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4758 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4769 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4770 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4789 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4790 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4795 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4808 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4816 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4817 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4818 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4820 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4821 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4822 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4823 static_cast<ARMOperand*>(Operands[4])->getReg())))
4829 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4835 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4836 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4850 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4851 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4872 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4874 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5126 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5127 MRC.contains(Op2->getReg())) {
5128 unsigned Reg1 = Op1->getReg();
5129 unsigned Reg2 = Op2->getReg();
5157 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5159 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5182 unsigned OpReg = Inst.getOperand(i).getReg();
5196 unsigned OpReg = Inst.getOperand(i).getReg();
5259 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5260 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5268 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5269 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5278 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5279 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5303 unsigned Rn = Inst.getOperand(0).getReg();
5325 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5341 (((ARMOperand*)Operands[3])->getReg() !=
5342 ((ARMOperand*)Operands[5])->getReg()) &&
5343 (((ARMOperand*)Operands[3])->getReg() !=
5344 ((ARMOperand*)Operands[4])->getReg())) {
5380 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5657 if (Inst.getOperand(1).getReg() != ARM::PC ||
5658 Inst.getOperand(5).getReg() != 0)
5728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5920 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5966 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6012 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6019 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6039 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6041 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6048 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6050 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6072 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6074 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6126 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6153 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6155 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6197 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6272 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6292 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6294 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6296 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6303 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6347 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6371 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6418 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6442 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6491 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6493 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6594 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6598 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6625 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6671 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6722 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6748 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6763 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6764 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6796 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6797 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6798 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6799 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6832 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6833 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7044 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7045 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7047 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7048 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7069 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7070 Inst.getOperand(5).getReg() != 0 ||
7087 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7127 unsigned Rn = Inst.getOperand(0).getReg();
7142 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7151 unsigned Rn = Inst.getOperand(0).getReg();
7189 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7192 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7193 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7212 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7213 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7215 Inst.getOperand(4).getReg() == ARM::CPSR &&
7220 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7236 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7237 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7348 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7349 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7350 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7351 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7352 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7386 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7387 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7388 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7389 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7390 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7391 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7406 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7441 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7445 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7448 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7455 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7456 isARMLowRegister(Inst.getOperand(2).getReg()))
7460 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7461 isARMLowRegister(Inst.getOperand(1).getReg()))
