Lines Matching full:absaddr
2681 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2683 ") ")#mnemonic#"(##$absaddr) = $src2",
2701 (ins u0AlwaysExt:$absaddr, RC:$src),
2702 mnemonic#"(##$absaddr) = $src",
2717 (ins PredRegs:$src1, u0AlwaysExt:$absaddr, RC: $src2),
2719 ") ")#mnemonic#"(##$absaddr) = $src2.new",
2737 (ins u0AlwaysExt:$absaddr, RC:$src),
2738 mnemonic#"(##$absaddr) = $src.new",
2768 (HexagonCONST32 tglobaladdr:$absaddr)),
2769 (STrib_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2772 (HexagonCONST32 tglobaladdr:$absaddr)),
2773 (STrih_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2775 def : Pat<(store (i32 IntRegs:$src1), (HexagonCONST32 tglobaladdr:$absaddr)),
2776 (STriw_abs_V4 tglobaladdr: $absaddr, IntRegs: $src1)>;
2779 (HexagonCONST32 tglobaladdr:$absaddr)),
2780 (STrid_abs_V4 tglobaladdr: $absaddr, DoubleRegs: $src1)>;
2891 (ins PredRegs:$src1, u0AlwaysExt:$absaddr),
2893 ") ")#"$dst = "#mnemonic#"(##$absaddr)",
2911 (ins u0AlwaysExt:$absaddr),
2912 "$dst = "#mnemonic#"(##$absaddr)",
2940 def : Pat<(i32 (load (HexagonCONST32 tglobaladdr:$absaddr))),
2941 (LDriw_abs_V4 tglobaladdr: $absaddr)>;
2943 def : Pat<(i32 (sextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2944 (LDrib_abs_V4 tglobaladdr:$absaddr)>;
2946 def : Pat<(i32 (zextloadi8 (HexagonCONST32 tglobaladdr:$absaddr))),
2947 (LDriub_abs_V4 tglobaladdr:$absaddr)>;
2949 def : Pat<(i32 (sextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2950 (LDrih_abs_V4 tglobaladdr:$absaddr)>;
2952 def : Pat<(i32 (zextloadi16 (HexagonCONST32 tglobaladdr:$absaddr))),
2953 (LDriuh_abs_V4 tglobaladdr:$absaddr)>;
