Lines Matching full:intid
20 class si_ALU32_sisi_not<string opc, Intrinsic IntID>
23 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
25 class di_ALU32_s8si<string opc, Intrinsic IntID>
28 [(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
30 class di_ALU32_sis8<string opc, Intrinsic IntID>
33 [(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
35 class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
38 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
40 class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
43 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
45 class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
48 [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
50 class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
53 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
55 class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
58 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
60 class si_ALU32_sis8<string opc, Intrinsic IntID>
63 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
69 class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
72 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
74 class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
79 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
82 class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
87 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
90 class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
95 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
98 class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
103 [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
106 class si_SInst_si_addsis6<string opc, Intrinsic IntID>
110 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
113 class si_SInst_si_subs6si<string opc, Intrinsic IntID>
117 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
120 class di_ALU64_didi_neg<string opc, Intrinsic IntID>
123 [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
125 class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
129 [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
133 class si_MInst_sisisi_and<string opc, Intrinsic IntID>
137 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
140 class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
144 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
147 class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
151 [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
154 class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
158 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
161 class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
165 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
168 class si_SInst_sisis10_or<string opc, Intrinsic IntID>
171 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
174 class si_MInst_sisisi_or<string opc, Intrinsic IntID>
178 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
181 class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
185 [(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
188 class si_SInst_siu5_sat<string opc, Intrinsic IntID>
191 [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
