Lines Matching refs:ISD
107 return DAG.getNode(ISD::ADD, DL, Ty,
124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
143 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
241 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
245 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
247 setOperationAction(ISD::SELECT, MVT::f32, Custom);
248 setOperationAction(ISD::SELECT, MVT::f64, Custom);
249 setOperationAction(ISD::SELECT, MVT::i32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
251 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
252 setOperationAction(ISD::SETCC, MVT::f32, Custom);
253 setOperationAction(ISD::SETCC, MVT::f64, Custom);
254 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
255 setOperationAction(ISD::VASTART, MVT::Other, Custom);
256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
261 setOperationAction(ISD::FABS, MVT::f32, Custom);
262 setOperationAction(ISD::FABS, MVT::f64, Custom);
266 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
268 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
269 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
270 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
271 setOperationAction(ISD::SELECT, MVT::i64, Custom);
272 setOperationAction(ISD::LOAD, MVT::i64, Custom);
273 setOperationAction(ISD::STORE, MVT::i64, Custom);
274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
278 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
279 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
283 setOperationAction(ISD::ADD, MVT::i32, Custom);
285 setOperationAction(ISD::ADD, MVT::i64, Custom);
287 setOperationAction(ISD::SDIV, MVT::i32, Expand);
288 setOperationAction(ISD::SREM, MVT::i32, Expand);
289 setOperationAction(ISD::UDIV, MVT::i32, Expand);
290 setOperationAction(ISD::UREM, MVT::i32, Expand);
291 setOperationAction(ISD::SDIV, MVT::i64, Expand);
292 setOperationAction(ISD::SREM, MVT::i64, Expand);
293 setOperationAction(ISD::UDIV, MVT::i64, Expand);
294 setOperationAction(ISD::UREM, MVT::i64, Expand);
297 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
298 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
299 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
300 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
301 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
302 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
304 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
305 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
307 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
308 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
309 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
310 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
311 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
313 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
314 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
315 setOperationAction(ISD::ROTL, MVT::i32, Expand);
316 setOperationAction(ISD::ROTL, MVT::i64, Expand);
317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
321 setOperationAction(ISD::ROTR, MVT::i32, Expand);
324 setOperationAction(ISD::ROTR, MVT::i64, Expand);
326 setOperationAction(ISD::FSIN, MVT::f32, Expand);
327 setOperationAction(ISD::FSIN, MVT::f64, Expand);
328 setOperationAction(ISD::FCOS, MVT::f32, Expand);
329 setOperationAction(ISD::FCOS, MVT::f64, Expand);
330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
331 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
332 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
333 setOperationAction(ISD::FPOW, MVT::f32, Expand);
334 setOperationAction(ISD::FPOW, MVT::f64, Expand);
335 setOperationAction(ISD::FLOG, MVT::f32, Expand);
336 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
337 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
338 setOperationAction(ISD::FEXP, MVT::f32, Expand);
339 setOperationAction(ISD::FMA, MVT::f32, Expand);
340 setOperationAction(ISD
341 setOperationAction(ISD::FREM, MVT::f32, Expand);
342 setOperationAction(ISD::FREM, MVT::f64, Expand);
345 setOperationAction(ISD::FNEG, MVT::f32, Expand);
346 setOperationAction(ISD::FNEG, MVT::f64, Expand);
349 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
351 setOperationAction(ISD::VAARG, MVT::Other, Expand);
352 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
353 setOperationAction(ISD::VAEND, MVT::Other, Expand);
356 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
357 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
359 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
360 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
361 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
362 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
372 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
373 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
377 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
378 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
382 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
383 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
384 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
388 setOperationAction(ISD::TRAP, MVT::Other, Legal);
390 setTargetDAGCombine(ISD::SDIVREM);
391 setTargetDAGCombine(ISD::UDIVREM);
392 setTargetDAGCombine(ISD::SELECT);
393 setTargetDAGCombine(ISD::AND);
394 setTargetDAGCombine(ISD::OR);
395 setTargetDAGCombine(ISD::ADD);
429 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
457 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
460 case ISD::SETEQ:
461 case ISD::SETOEQ: return Mips::FCOND_OEQ;
462 case ISD::SETUNE: return Mips::FCOND_UNE;
463 case ISD::SETLT:
464 case ISD::SETOLT: return Mips::FCOND_OLT;
465 case ISD::SETGT:
466 case ISD::SETOGT: return Mips::FCOND_OGT;
467 case ISD::SETLE:
468 case ISD::SETOLE: return Mips::FCOND_OLE;
469 case ISD::SETGE:
470 case ISD::SETOGE: return Mips::FCOND_OGE;
471 case ISD::SETULT: return Mips::FCOND_ULT;
472 case ISD::SETULE: return Mips::FCOND_ULE;
473 case ISD::SETUGT: return Mips::FCOND_UGT;
474 case ISD::SETUGE: return Mips::FCOND_UGE;
475 case ISD::SETUO: return Mips::FCOND_UN;
476 case ISD::SETO: return Mips::FCOND_OR;
477 case ISD::SETNE:
478 case ISD::SETONE: return Mips::FCOND_ONE;
479 case ISD::SETUEQ: return Mips::FCOND_UEQ;
500 if (Op.getOpcode() != ISD::SETCC)
513 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
538 if ((SetCC.getOpcode() != ISD::SETCC) ||
554 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
558 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
560 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
576 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
618 if (And0.getOpcode() != ISD::AND)
626 if (And1.getOpcode() != ISD::AND)
638 if (Shl.getOpcode() != ISD::SHL)
667 if (Add.getOpcode() != ISD::ADD)
673 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
679 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
681 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
691 case ISD::SDIVREM:
692 case ISD::UDIVREM:
694 case ISD::SELECT:
696 case ISD::AND:
698 case ISD::OR:
700 case ISD::ADD:
729 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
730 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
731 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
732 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
733 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
734 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
735 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
736 case ISD::SELECT: return lowerSELECT(Op, DAG);
737 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
738 case ISD::SETCC: return lowerSETCC(Op, DAG);
739 case ISD::VASTART: return lowerVASTART(Op, DAG);
740 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
741 case ISD::FABS: return lowerFABS(Op, DAG);
742 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
743 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
744 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
745 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
746 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
747 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
748 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
749 case ISD::LOAD: return lowerLOAD(Op, DAG);
750 case ISD::STORE: return lowerSTORE(Op, DAG);
751 case ISD::ADD: return lowerADD(Op, DAG);
752 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1403 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1405 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1408 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1417 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1421 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1467 SDValue Cond = DAG.getNode(ISD::SETCC, DL,
1472 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1505 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1582 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1583 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1605 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1609 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1632 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1666 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1670 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1685 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1686 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1687 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1688 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1689 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1693 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1708 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1709 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1718 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1720 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1724 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1732 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1733 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1734 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1738 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1740 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1742 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1744 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1745 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1763 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1773 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1774 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1778 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1790 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1798 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1799 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1802 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1895 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1897 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1899 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1901 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1902 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1903 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1904 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1906 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1908 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1933 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1935 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
1937 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
1938 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
1939 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1940 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1942 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1944 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
1946 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
1947 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
1964 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
1984 ISD::LoadExtType ExtType = LD->getExtensionType();
1994 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2013 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2014 (ExtType == ISD::EXTLOAD))
2017 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2028 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2029 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2042 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2083 if (Val.getOpcode() != ISD::FP_TO_SINT)
2108 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2111 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2124 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr,
2133 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2157 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2257 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2330 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2332 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2392 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2415 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2432 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2435 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2438 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2452 // emit ISD::STORE whichs stores the
2461 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2528 const SmallVectorImpl<ISD::InputArg> &Ins,
2550 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2567 const SmallVectorImpl<ISD::InputArg> &Ins,
2601 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2643 Opcode = ISD::AssertSext;
2645 Opcode = ISD::AssertZext;
2649 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2657 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2697 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2707 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2721 const SmallVectorImpl<ISD::OutputArg> &Outs,
2732 const SmallVectorImpl<ISD::OutputArg> &Outs,
2759 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
3146 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3157 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3184 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3192 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3227 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3241 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3247 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3256 ISD::ArgFlagsTy ArgFlags) {
3345 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3377 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3393 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3407 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3435 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3438 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3451 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3455 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3472 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3474 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
