Lines Matching refs:Mips
1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
14 #define DEBUG_TYPE "mips-lower"
44 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
48 cl::desc("MIPS: Don't trap on integer division by zero."),
52 Mips::A0, Mips::A1, Mips::A2, Mips::A3
56 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
57 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
61 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
62 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
220 // Mips does not have i1 type, so use i32 for
230 // MIPS doesn't have extending float->double load/store
240 // Mips Custom Operations
296 // Operations not directly supported by Mips.
399 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
401 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
402 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
427 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
428 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
457 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
461 case ISD::SETOEQ: return Mips::FCOND_OEQ;
462 case ISD::SETUNE: return Mips::FCOND_UNE;
464 case ISD::SETOLT: return Mips::FCOND_OLT;
466 case ISD::SETOGT: return Mips::FCOND_OGT;
468 case ISD::SETOLE: return Mips::FCOND_OLE;
470 case ISD::SETOGE: return Mips::FCOND_OGE;
471 case ISD::SETULT: return Mips::FCOND_ULT;
472 case ISD::SETULE: return Mips::FCOND_ULE;
473 case ISD::SETUGT: return Mips::FCOND_UGT;
474 case ISD::SETUGE: return Mips::FCOND_UGE;
475 case ISD::SETUO: return Mips::FCOND_UN;
476 case ISD::SETO: return Mips::FCOND_OR;
478 case ISD::SETONE: return Mips::FCOND_ONE;
479 case ISD::SETUEQ: return Mips::FCOND_UEQ;
486 static bool invertFPCondCodeUser(Mips::CondCode CC) {
487 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
490 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
523 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
524 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
782 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
783 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7);
787 MIB->getOperand(0).setSubReg(Mips::sub_32);
798 case Mips::ATOMIC_LOAD_ADD_I8:
799 case Mips::ATOMIC_LOAD_ADD_I8_P8:
800 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
801 case Mips::ATOMIC_LOAD_ADD_I16:
802 case Mips::ATOMIC_LOAD_ADD_I16_P8:
803 Mips::ADDu);
804 case Mips::ATOMIC_LOAD_ADD_I32:
805 case Mips::ATOMIC_LOAD_ADD_I32_P8:
806 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
807 case Mips::ATOMIC_LOAD_ADD_I64:
808 case Mips::ATOMIC_LOAD_ADD_I64_P8:
809 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
811 case Mips::ATOMIC_LOAD_AND_I8:
812 case Mips::ATOMIC_LOAD_AND_I8_P8:
813 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
814 case Mips::ATOMIC_LOAD_AND_I16:
815 case Mips::ATOMIC_LOAD_AND_I16_P8:
816 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
817 case Mips::ATOMIC_LOAD_AND_I32:
818 case Mips::ATOMIC_LOAD_AND_I32_P8:
819 return emitAtomicBinary(MI, BB, 4, Mips::AND);
820 case Mips::ATOMIC_LOAD_AND_I64:
821 case Mips::ATOMIC_LOAD_AND_I64_P8:
822 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
824 case Mips::ATOMIC_LOAD_OR_I8:
825 case Mips::ATOMIC_LOAD_OR_I8_P8:
826 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
827 case Mips::ATOMIC_LOAD_OR_I16:
828 case Mips::ATOMIC_LOAD_OR_I16_P8:
829 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
830 case Mips::ATOMIC_LOAD_OR_I32:
831 case Mips::ATOMIC_LOAD_OR_I32_P8:
832 return emitAtomicBinary(MI, BB, 4, Mips::OR);
833 case Mips::ATOMIC_LOAD_OR_I64:
834 case Mips::ATOMIC_LOAD_OR_I64_P8:
835 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
837 case Mips::ATOMIC_LOAD_XOR_I8:
838 case Mips::ATOMIC_LOAD_XOR_I8_P8:
839 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
840 case Mips::ATOMIC_LOAD_XOR_I16:
841 case Mips::ATOMIC_LOAD_XOR_I16_P8:
842 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
843 case Mips::ATOMIC_LOAD_XOR_I32:
844 case Mips::ATOMIC_LOAD_XOR_I32_P8:
845 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
846 case Mips::ATOMIC_LOAD_XOR_I64:
847 case Mips::ATOMIC_LOAD_XOR_I64_P8:
848 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
850 case Mips::ATOMIC_LOAD_NAND_I8:
851 case Mips::ATOMIC_LOAD_NAND_I8_P8:
853 case Mips::ATOMIC_LOAD_NAND_I16:
854 case Mips::ATOMIC_LOAD_NAND_I16_P8:
856 case Mips::ATOMIC_LOAD_NAND_I32:
857 case Mips::ATOMIC_LOAD_NAND_I32_P8:
859 case Mips::ATOMIC_LOAD_NAND_I64:
860 case Mips::ATOMIC_LOAD_NAND_I64_P8:
863 case Mips::ATOMIC_LOAD_SUB_I8:
864 case Mips::ATOMIC_LOAD_SUB_I8_P8:
865 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
866 case Mips::ATOMIC_LOAD_SUB_I16:
867 case Mips::ATOMIC_LOAD_SUB_I16_P8:
868 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
869 case Mips::ATOMIC_LOAD_SUB_I32:
870 case Mips::ATOMIC_LOAD_SUB_I32_P8:
871 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
872 case Mips::ATOMIC_LOAD_SUB_I64:
873 case Mips::ATOMIC_LOAD_SUB_I64_P8:
874 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
876 case Mips::ATOMIC_SWAP_I8:
877 case Mips::ATOMIC_SWAP_I8_P8:
879 case Mips::ATOMIC_SWAP_I16:
880 case Mips::ATOMIC_SWAP_I16_P8:
882 case Mips::ATOMIC_SWAP_I32:
883 case Mips::ATOMIC_SWAP_I32_P8:
885 case Mips::ATOMIC_SWAP_I64:
886 case Mips::ATOMIC_SWAP_I64_P8:
889 case Mips::ATOMIC_CMP_SWAP_I8:
890 case Mips::ATOMIC_CMP_SWAP_I8_P8:
892 case Mips::ATOMIC_CMP_SWAP_I16:
893 case Mips::ATOMIC_CMP_SWAP_I16_P8:
895 case Mips::ATOMIC_CMP_SWAP_I32:
896 case Mips::ATOMIC_CMP_SWAP_I32_P8:
898 case Mips::ATOMIC_CMP_SWAP_I64:
899 case Mips::ATOMIC_CMP_SWAP_I64_P8:
901 case Mips::PseudoSDIV:
902 case Mips::PseudoUDIV:
904 case Mips::PseudoDSDIV:
905 case Mips::PseudoDUDIV:
910 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
911 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
926 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
927 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
928 AND = Mips::AND;
929 NOR = Mips::NOR;
930 ZERO = Mips::ZERO;
931 BEQ = Mips::BEQ;
934 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
935 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
936 AND = Mips::AND64;
937 NOR = Mips::NOR64;
938 ZERO = Mips::ZERO_64;
939 BEQ = Mips::BEQ64;
1011 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1012 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1069 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1070 .addReg(Mips::ZERO).addImm(-4);
1071 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1073 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1075 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1078 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1080 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1082 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1083 .addReg(Mips::ZERO).addImm(MaskImm);
1084 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1086 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1087 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1114 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1115 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1116 .addReg(Mips::ZERO).addReg(AndRes);
1117 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1122 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1125 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1128 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1130 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1134 BuildMI(BB, DL, TII->get(Mips::BEQ))
1135 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1145 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1147 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1149 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1151 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1173 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1174 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1175 ZERO = Mips::ZERO;
1176 BNE = Mips::BNE;
1177 BEQ = Mips::BEQ;
1180 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1181 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1182 ZERO = Mips::ZERO_64;
1183 BNE = Mips::BNE64;
1184 BEQ = Mips::BEQ64;
1253 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1254 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1319 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1320 .addReg(Mips::ZERO).addImm(-4);
1321 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1323 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1325 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1328 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1330 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1332 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1333 .addReg(Mips::ZERO).addImm(MaskImm);
1334 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1336 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1337 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1339 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1341 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1343 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1352 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1354 BuildMI(BB, DL, TII->get(Mips::BNE))
1363 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1365 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1369 BuildMI(BB, DL, TII->get(Mips::BEQ))
1370 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1379 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1381 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes)
1383 BuildMI(BB, DL, TII->get(Mips::SRA), Dest)
1440 Mips::CondCode CC =
1441 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1442 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1444 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1504 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32);
1770 DAG.getRegister(Mips::ZERO, MVT::i32),
1795 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1824 IsN64 ? Mips::FP_64 : Mips::FP, VT);
1837 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA;
1863 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1;
1864 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0;
2142 // Mips O32 ABI rules:
2162 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2165 Mips::F12, Mips::F14
2168 Mips::D6, Mips::D7
2200 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2205 // available register is Mips::A1 or Mips::A3, shadow it too.
2207 if (Reg == Mips::A1 || Reg == Mips::A3)
2221 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2248 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2249 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2281 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2379 IsN64 ? Mips::SP_64 : Mips::SP,
2621 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass :
2622 &Mips::GPR32RegClass;
2624 RC = &Mips::GPR64RegClass;
2626 RC = &Mips::FGR32RegClass;
2628 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
2686 // The mips ABIs for returning structs by value requires that we copy
2768 // The mips ABIs for returning structs by value requires that we copy
2779 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0;
2792 // Return on Mips is always a "jr $ra"
2797 // Mips Inline Assembly Support
2805 // Mips specific constrainy
2806 // GCC config/mips/constraints.md
2896 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
2897 return std::make_pair(0U, &Mips::GPR32RegClass);
2900 return std::make_pair(0U, &Mips::GPR32RegClass);
2902 return std::make_pair(0U, &Mips::GPR64RegClass);
2907 return std::make_pair(0U, &Mips::FGR32RegClass);
2910 return std::make_pair(0U, &Mips::FGR64RegClass);
2911 return std::make_pair(0U, &Mips::AFGR64RegClass);
2916 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
2918 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
2921 return std::make_pair((unsigned)Mips::LO, &Mips::LORegsRegClass);
2922 return std::make_pair((unsigned)Mips::LO64, &Mips::LORegs64RegClass);
3049 // The Mips target isn't yet aware of offsets.
