Lines Matching refs:Mips
19 #define DEBUG_TYPE "mips-long-branch"
21 #include "Mips.h"
39 "skip-mips-long-branch",
41 cl::desc("MIPS: Skip long branch pass."),
45 "force-mips-long-branch",
47 cl::desc("MIPS: Expand all branches to long format."),
73 return "Mips Long Branch";
288 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
289 .addReg(Mips::SP).addImm(-8);
290 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
291 .addReg(Mips::SP).addImm(0);
294 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
295 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
299 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
300 .addReg(Mips::AT).addImm(Lo);
301 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
302 .addReg(Mips::RA).addReg(Mips::AT);
303 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
304 .addReg(Mips::SP).addImm(0);
307 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
308 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
309 .addReg(Mips::SP).addImm(8));
335 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
336 .addReg(Mips::SP_64).addImm(-16);
337 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
338 .addReg(Mips::SP_64).addImm(0);
339 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi64), Mips::AT_64)
341 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
342 .addReg(Mips::AT_64).addImm(Higher);
343 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
344 .addReg(Mips::AT_64).addImm(16);
345 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
346 .addReg(Mips::AT_64).addImm(Hi);
349 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
350 .append(BuildMI(*MF, DL, TII->get(Mips::DSLL), Mips::AT_64)
351 .addReg(Mips::AT_64).addImm(16));
355 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
356 .addReg(Mips::AT_64).addImm(Lo);
357 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
358 .addReg(Mips::RA_64).addReg(Mips::AT_64);
359 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
360 .addReg(Mips::SP_64).addImm(0);
363 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
364 .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
365 .addReg(Mips::SP_64).addImm(16));
379 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
380 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
399 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
401 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
402 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
403 MBB.removeLiveIn(Mips::V0);
