Lines Matching full:registerclass
227 RegisterClass<"Mips", regTypes, 32, (add
244 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
258 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
264 def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
271 def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
273 def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
282 def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
284 def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
296 def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
299 def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
303 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
307 def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;
308 def HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>;
309 def LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>;
310 def HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>;
311 def LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>;
312 def HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>;
315 def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable;
316 def HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable;
319 def ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
323 def ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
327 def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
331 def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
