Lines Matching refs:Mips
14 #define DEBUG_TYPE "mips-isel"
16 #include "Mips.h"
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
74 if ((MI.getOpcode() == Mips::ADDiu) &&
75 (MI.getOperand(1).getReg() == Mips::ZERO) &&
78 ZeroReg = Mips::ZERO;
79 } else if ((MI.getOpcode() == Mips::DADDiu) &&
80 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
83 ZeroReg = Mips::ZERO_64;
122 RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
124 RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
130 MF.getRegInfo().addLiveIn(Mips::T9_64);
131 MBB.addLiveIn(Mips::T9_64);
137 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
139 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
140 .addReg(Mips::T9_64);
141 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
151 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
153 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
158 MF.getRegInfo().addLiveIn(Mips::T9);
159 MBB.addLiveIn(Mips::T9);
166 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
168 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
169 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
190 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
193 MF.getRegInfo().addLiveIn(Mips::V0);
194 MBB.addLiveIn(Mips::V0);
195 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
196 .addReg(Mips::V0).addReg(Mips::T9);
207 if (I->getOpcode() == Mips::RDDSP)
209 else if (I->getOpcode() == Mips::WRDSP)
229 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
230 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
237 /// Used on Mips Load/Store instructions
332 Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
340 Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
349 Mips::ZERO_64, MVT::i64);
350 Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
353 Mips::ZERO, MVT::i32);
354 Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
385 if (Inst->Opc == Mips::LUi64)
390 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
409 RdhwrOpc = Mips::RDHWR;
410 SrcReg = Mips::HWR29;
411 DestReg = Mips::V1;
413 RdhwrOpc = Mips::RDHWR64;
414 SrcReg = Mips::HWR29_64;
415 DestReg = Mips::V1_64;
430 unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
431 Mips::ACRegsRegClassID;
433 SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
434 SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
