Lines Matching refs:ISD
46 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
49 setOperationAction(ISD::ADD, VecTys[i], Legal);
50 setOperationAction(ISD::SUB, VecTys[i], Legal);
51 setOperationAction(ISD::LOAD, VecTys[i], Legal);
52 setOperationAction(ISD::STORE, VecTys[i], Legal);
53 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
65 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
66 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand);
67 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand);
70 setTargetDAGCombine(ISD::SHL);
71 setTargetDAGCombine(ISD::SRA);
72 setTargetDAGCombine(ISD::SRL);
73 setTargetDAGCombine(ISD::SETCC);
74 setTargetDAGCombine(ISD::VSELECT);
78 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
92 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
94 setOperationAction(ISD::MULHS, MVT::i32, Custom);
95 setOperationAction(ISD::MULHU, MVT::i32, Custom);
98 setOperationAction(ISD::MULHS, MVT::i64, Custom);
99 setOperationAction(ISD::MULHU, MVT::i64, Custom);
100 setOperationAction(ISD::MUL, MVT::i64, Custom);
103 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
104 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
106 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
107 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
108 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
109 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
110 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
111 setOperationAction(ISD::LOAD, MVT::i32, Custom);
112 setOperationAction(ISD::STORE, MVT::i32, Custom);
114 setTargetDAGCombine(ISD::ADDE);
115 setTargetDAGCombine(ISD::SUBE);
116 setTargetDAGCombine(ISD::MUL);
145 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
146 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
147 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
148 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
149 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
150 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
151 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
153 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
154 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
173 if (ADDCNode->getOpcode() != ISD::ADDC)
186 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
212 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
249 if (SUBCNode->getOpcode() != ISD::SUBC)
262 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
288 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
353 return DAG.getNode(ISD::SHL, DL, VT, X,
366 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
373 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
444 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
448 case ISD::SETEQ:
449 case ISD
450 case ISD::SETLT:
451 case ISD::SETLE:
452 case ISD::SETGT:
453 case ISD::SETGE: return IsV216;
454 case ISD::SETULT:
455 case ISD::SETULE:
456 case ISD::SETUGT:
457 case ISD::SETUGE: return !IsV216;
497 case ISD::ADDE:
499 case ISD::SUBE:
501 case ISD::MUL:
503 case ISD::SHL:
505 case ISD::SRA:
507 case ISD::SRL:
509 case ISD::VSELECT:
511 case ISD::SETCC: {
592 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
594 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
604 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
630 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
