Lines Matching refs:Mips
25 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
26 cl::desc("MIPS: Enable tail calls."), cl::init(false));
34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
37 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
43 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass);
81 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
86 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
88 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
221 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
227 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
297 SDValue LoIdx = CurDAG->getConstant(Mips::sub_lo, MVT::i32);
303 SDValue HiIdx = CurDAG->getConstant(Mips::sub_hi, MVT::i32);
529 case Mips::BPOSGE32_PSEUDO:
558 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
578 DAG.getConstant(Mips::sub_lo, MVT::i32));
581 DAG.getConstant(Mips::sub_hi, MVT::i32));
601 DAG.getConstant(Mips::sub_lo, MVT::i32));
603 DAG.getConstant(Mips::sub_hi, MVT::i32));
607 // This function expands mips intrinsic nodes which have 64-bit input operands
614 // mips-specific-node
772 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
796 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
800 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
801 .addReg(Mips::ZERO).addImm(0);
802 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
806 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
807 .addReg(Mips::ZERO).addImm(1);
810 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
