Lines Matching full:srcreg
93 unsigned DestReg, unsigned SrcReg,
98 if (Mips::GPR32RegClass.contains(SrcReg))
100 else if (Mips::CCRRegClass.contains(SrcReg))
102 else if (Mips::FGR32RegClass.contains(SrcReg))
104 else if (Mips::HIRegsRegClass.contains(SrcReg))
105 Opc = Mips::MFHI, SrcReg = 0;
106 else if (Mips::LORegsRegClass.contains(SrcReg))
107 Opc = Mips::MFLO, SrcReg = 0;
108 else if (Mips::HIRegsDSPRegClass.contains(SrcReg))
110 else if (Mips::LORegsDSPRegClass.contains(SrcReg))
112 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
114 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
138 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
145 if (Mips::GPR64RegClass.contains(SrcReg))
147 else if (Mips::HIRegs64RegClass.contains(SrcReg))
148 Opc = Mips::MFHI64, SrcReg = 0;
149 else if (Mips::LORegs64RegClass.contains(SrcReg))
150 Opc = Mips::MFLO64, SrcReg = 0;
151 else if (Mips::FGR64RegClass.contains(SrcReg))
154 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
170 if (SrcReg)
171 MIB.addReg(SrcReg, getKillRegState(KillSrc));
179 unsigned SrcReg, bool isKill, int FI,
208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
408 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
422 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
429 unsigned SrcReg = I->getOperand(1).getReg();
436 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
