Lines Matching refs:Ins
74 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
498 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
824 if (Ins.size() > 0) {
880 Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, MVT::i32), InFlag
927 if (Ins.size() > 0) {
1057 assert(VTs.size() == Ins.size() && "Bad value decomposition");
1058 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1078 LoadRetVTs.push_back(Ins[i].VT);
1095 Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1362 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
1387 // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
1388 // Ins.size() will be larger
1390 // showing up separately in Ins)
1393 // individually present in Ins.
1394 // So a different index should be used for indexing into Ins.
1435 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1442 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
1479 if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
1480 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1482 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
1523 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
1524 P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
1548 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
1549 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
1550 Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
1592 if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
1593 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
1612 if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
1613 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
1615 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
1619 p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
1637 assert(ObjectVT == Ins[InsIdx].VT &&
1638 "Ins type did not match function type");
