Lines Matching full:fixups
48 SmallVectorImpl<MCFixup> &Fixups) const;
50 SmallVectorImpl<MCFixup> &Fixups) const;
52 SmallVectorImpl<MCFixup> &Fixups) const;
54 SmallVectorImpl<MCFixup> &Fixups) const;
56 SmallVectorImpl<MCFixup> &Fixups) const;
58 SmallVectorImpl<MCFixup> &Fixups) const;
60 SmallVectorImpl<MCFixup> &Fixups) const;
62 SmallVectorImpl<MCFixup> &Fixups) const;
64 SmallVectorImpl<MCFixup> &Fixups) const;
66 SmallVectorImpl<MCFixup> &Fixups) const;
71 SmallVectorImpl<MCFixup> &Fixups) const;
76 SmallVectorImpl<MCFixup> &Fixups) const;
78 SmallVectorImpl<MCFixup> &Fixups) const {
79 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
111 SmallVectorImpl<MCFixup> &Fixups) const {
113 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
116 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
122 SmallVectorImpl<MCFixup> &Fixups) const {
124 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
127 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
134 SmallVectorImpl<MCFixup> &Fixups) const {
136 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
139 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
146 SmallVectorImpl<MCFixup> &Fixups) const {
148 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
151 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
157 SmallVectorImpl<MCFixup> &Fixups) const {
159 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups);
162 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
168 SmallVectorImpl<MCFixup> &Fixups) const {
172 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16;
176 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits;
179 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
186 SmallVectorImpl<MCFixup> &Fixups) const {
190 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14;
194 return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits;
197 Fixups.push_back(MCFixup::Create(2, MO.getExpr(),
204 SmallVectorImpl<MCFixup> &Fixups) const {
206 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups);
211 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
217 SmallVectorImpl<MCFixup> &Fixups) const {
218 // For special TLS calls, we need two fixups; one for the branch target
222 Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
224 return getDirectBrEncoding(MI, OpNo, Fixups);
229 SmallVectorImpl<MCFixup> &Fixups) const {
240 SmallVectorImpl<MCFixup> &Fixups) const {
