Lines Matching refs:ISD
113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
126 if (N.getOpcode() == ISD::TargetConstant ||
127 N.getOpcode() == ISD::TargetGlobalAddress) {
282 if (N->getOpcode() != ISD::Constant)
300 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
310 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
371 if (Opcode == ISD::SHL) {
376 } else if (Opcode == ISD::SRL) {
383 } else if (Opcode == ISD::ROTL) {
421 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
422 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
423 Op0.getOperand(0).getOpcode() == ISD::SRL) {
424 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
425 Op1.getOperand(0).getOpcode() != ISD::SRL) {
431 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
432 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
433 Op1.getOperand(0).getOpcode() != ISD::SRL) {
444 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
447 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
449 if (Op1Opc == ISD::AND) {
451 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
456 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
472 ISD::CondCode CC, SDLoc dl) {
478 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
504 } else if (ISD::isUnsignedIntSetCC(CC)) {
519 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
547 } else if (ISD::isUnsignedIntSetCC(CC)) {
569 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
571 case ISD::SETUEQ:
572 case ISD::SETONE:
573 case ISD::SETOLE:
574 case ISD::SETOGE:
577 case ISD::SETOEQ:
578 case ISD::SETEQ: return PPC::PRED_EQ;
579 case ISD::SETUNE:
580 case ISD::SETNE: return PPC::PRED_NE;
581 case ISD::SETOLT:
582 case ISD::SETLT: return PPC::PRED_LT;
583 case ISD::SETULE:
584 case ISD::SETLE: return PPC::PRED_LE;
585 case ISD::SETOGT:
586 case ISD::SETGT: return PPC::PRED_GT;
587 case ISD::SETUGE:
588 case ISD::SETGE: return PPC::PRED_GE;
589 case ISD::SETO: return PPC::PRED_NU;
590 case ISD::SETUO: return PPC::PRED_UN;
592 case ISD::SETULT: return PPC::PRED_LT;
593 case ISD::SETUGT: return PPC::PRED_GT;
600 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
604 case ISD::SETOLT:
605 case ISD::SETLT: return 0; // Bit #0 = SETOLT
606 case ISD::SETOGT:
607 case ISD::SETGT: return 1; // Bit #1 = SETOGT
608 case ISD::SETOEQ:
609 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
610 case ISD::SETUO: return 3; // Bit #3 = SETUO
611 case ISD::SETUGE:
612 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
613 case ISD::SETULE:
614 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
615 case ISD::SETUNE:
616 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
617 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
618 case ISD::SETUEQ:
619 case ISD::SETOGE:
620 case ISD::SETOLE:
621 case ISD::SETONE:
624 case ISD::SETULT: return 0;
625 case ISD::SETUGT: return 1;
632 static unsigned int getVCmpInst(MVT::SimpleValueType VecVT, ISD::CondCode CC) {
634 case ISD::SETEQ:
635 case ISD::SETUEQ:
636 case ISD::SETNE:
637 case ISD::SETUNE:
648 case ISD::SETLT:
649 case ISD::SETGT:
650 case ISD::SETLE:
651 case ISD::SETGE:
661 case ISD::SETULT:
662 case ISD::SETUGT:
663 case ISD::SETUGE:
664 case ISD::SETULE:
672 case ISD::SETOEQ:
676 case ISD::SETOLT:
677 case ISD::SETOGT:
678 case ISD::SETOLE:
682 case ISD::SETOGE:
714 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
726 case ISD::SETEQ: {
731 case ISD::SETNE: {
739 case ISD::SETLT: {
743 case ISD::SETGT: {
755 case ISD::SETEQ:
764 case ISD::SETNE: {
772 case ISD::SETLT: {
780 case ISD::SETGT: {
802 case ISD::SETEQ:
803 case ISD::SETOEQ:
804 case ISD::SETUEQ:
806 case ISD::SETNE:
807 case ISD::SETONE:
808 case ISD::SETUNE: {
812 case ISD::SETLT:
813 case ISD::SETOLT:
814 case ISD::SETULT:
816 case ISD::SETGT:
817 case ISD::SETOGT:
818 case ISD::SETUGT:
820 case ISD::SETGE:
821 case ISD::SETOGE:
822 case ISD::SETUGE: {
835 case ISD::SETLE:
836 case ISD::SETOLE:
837 case ISD::SETULE: {
885 case ISD::Constant: {
960 case ISD::SETCC:
965 case ISD::FrameIndex: {
982 case ISD::SDIV: {
1013 case ISD::LOAD: {
1019 if (LD->getAddressingMode() != ISD::PRE_INC)
1023 if (Offset.getOpcode() == ISD::TargetConstant ||
1024 Offset.getOpcode() == ISD::TargetGlobalAddress) {
1027 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1061 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
1097 case ISD::AND: {
1113 N->getOperand(0).getOpcode() != ISD::ROTL) {
1131 // ISD::OR doesn't get all the bitfield insertion fun.
1134 N->getOperand(0).getOpcode() == ISD::OR &&
1149 case ISD::OR:
1156 case ISD::SHL: {
1158 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1168 case ISD::SRL: {
1170 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1180 case ISD::SELECT_CC: {
1181 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1191 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1243 case ISD::BR_CC: {
1244 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1250 case ISD::BRIND: {
