Lines Matching defs:PVT
6061 MVT PVT = getPointerTy();
6062 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6105 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6106 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6107 const int64_t BPOffset = 4 * PVT.getStoreSize();
6110 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6199 MVT PVT = getPointerTy();
6200 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6204 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6207 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6208 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6209 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6213 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6214 const int64_t SPOffset = 2 * PVT.getStoreSize();
6215 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6216 const int64_t BPOffset = 4 * PVT.getStoreSize();
6223 if (PVT == MVT::i64) {
6235 if (PVT == MVT::i64) {
6247 if (PVT == MVT::i64) {
6259 if (PVT == MVT::i64) {
6271 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6281 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6282 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
