Lines Matching refs:ISD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
158 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
160 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
167 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
168 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
171 setOperationAction(ISD::FRINT, MVT::f64, Legal);
172 setOperationAction(ISD::FRINT, MVT::f32, Legal);
177 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
181 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
183 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
184 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
187 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
188 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
190 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
191 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
195 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
196 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
199 setOperationAction(ISD::SELECT, MVT::i32, Expand);
200 setOperationAction(ISD::SELECT, MVT::i64, Expand);
201 setOperationAction(ISD::SELECT, MVT::f32, Expand);
202 setOperationAction(ISD::SELECT, MVT::f64, Expand);
205 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
206 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
209 setOperationAction(ISD::SETCC, MVT::i32, Custom);
212 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
214 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
217 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
220 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
221 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
223 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
224 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
225 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
226 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
237 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
238 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
244 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
245 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
246 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
247 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
248 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
249 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
250 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
251 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
254 setOperationAction(ISD::TRAP, MVT::Other, Legal);
257 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
258 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
261 setOperationAction(ISD::VASTART , MVT::Other, Custom);
266 setOperationAction(ISD::VAARG, MVT::i1, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i8, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::i16, Promote);
271 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
272 setOperationAction(ISD::VAARG, MVT::i32, Promote);
273 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
274 setOperationAction(ISD::VAARG, MVT::Other, Expand);
277 setOperationAction(ISD::VAARG, MVT::Other, Custom);
278 setOperationAction(ISD::VAARG, MVT::i64, Custom);
281 setOperationAction(ISD::VAARG, MVT::Other, Expand);
285 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
287 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
290 setOperationAction(ISD::VAEND , MVT::Other, Expand);
291 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
292 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
293 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
294 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
297 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
300 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
303 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
311 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
318 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
319 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
320 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
321 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
324 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
327 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
330 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
336 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
337 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
338 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
339 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
343 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
345 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
352 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
354 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
355 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
356 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
359 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
360 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
361 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
372 setOperationAction(ISD::ADD , VT, Legal);
373 setOperationAction(ISD::SUB , VT, Legal);
376 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
377 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
380 ISD::AND , VT, Promote);
381 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
382 setOperationAction(ISD::OR , VT, Promote);
383 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
384 setOperationAction(ISD::XOR , VT, Promote);
385 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
386 setOperationAction(ISD::LOAD , VT, Promote);
387 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
388 setOperationAction(ISD::SELECT, VT, Promote);
389 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
390 setOperationAction(ISD::STORE, VT, Promote);
391 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
394 setOperationAction(ISD::MUL , VT, Expand);
395 setOperationAction(ISD::SDIV, VT, Expand);
396 setOperationAction(ISD::SREM, VT, Expand);
397 setOperationAction(ISD::UDIV, VT, Expand);
398 setOperationAction(ISD::UREM, VT, Expand);
399 setOperationAction(ISD::FDIV, VT, Expand);
400 setOperationAction(ISD::FREM, VT, Expand);
401 setOperationAction(ISD::FNEG, VT, Expand);
402 setOperationAction(ISD::FSQRT, VT, Expand);
403 setOperationAction(ISD::FLOG, VT, Expand);
404 setOperationAction(ISD::FLOG10, VT, Expand);
405 setOperationAction(ISD::FLOG2, VT, Expand);
406 setOperationAction(ISD::FEXP, VT, Expand);
407 setOperationAction(ISD::FEXP2, VT, Expand);
408 setOperationAction(ISD::FSIN, VT, Expand);
409 setOperationAction(ISD::FCOS, VT, Expand);
410 setOperationAction(ISD::FABS, VT, Expand);
411 setOperationAction(ISD::FPOWI, VT, Expand);
412 setOperationAction(ISD::FFLOOR, VT, Expand);
413 setOperationAction(ISD::FCEIL, VT, Expand);
414 setOperationAction(ISD::FTRUNC, VT, Expand);
415 setOperationAction(ISD::FRINT, VT, Expand);
416 setOperationAction(ISD::FNEARBYINT, VT, Expand);
417 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
418 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
419 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
420 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
421 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
422 setOperationAction(ISD::UDIVREM, VT, Expand);
423 setOperationAction(ISD::SDIVREM, VT, Expand);
424 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
425 setOperationAction(ISD::FPOW, VT, Expand);
426 setOperationAction(ISD::CTPOP, VT, Expand);
427 setOperationAction(ISD::CTLZ, VT, Expand);
428 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
429 setOperationAction(ISD::CTTZ, VT, Expand);
430 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
431 setOperationAction(ISD::VSELECT, VT, Expand);
432 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
439 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
440 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
441 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
446 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
448 setOperationAction(ISD::AND , MVT::v4i32, Legal);
449 setOperationAction(ISD::OR , MVT::v4i32, Legal);
450 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
451 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
452 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
453 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
454 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
455 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
456 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
457 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
458 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
459 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
460 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
461 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
468 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
472 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
473 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
476 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
477 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
478 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
480 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
481 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
483 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
485 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
486 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
489 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
491 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
494 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
496 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
497 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
501 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
502 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
506 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
507 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
508 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
525 setTargetDAGCombine(ISD::SINT_TO_FP);
526 setTargetDAGCombine(ISD::LOAD);
527 setTargetDAGCombine(ISD::STORE);
528 setTargetDAGCombine(ISD::BR_CC);
529 setTargetDAGCombine(ISD::BSWAP);
530 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
534 setTargetDAGCombine(ISD::FDIV);
535 setTargetDAGCombine(ISD::FSQRT);
681 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
878 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
924 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
962 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
980 if (N->getOpcode() != ISD::Constant)
1001 if (N.getOpcode() == ISD::ADD) {
1010 } else if (N.getOpcode() == ISD::OR) {
1092 if (N.getOpcode() == ISD::ADD) {
1109 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1110 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1111 Disp.getOpcode() == ISD::TargetConstantPool ||
1112 Disp.getOpcode() == ISD::TargetJumpTable);
1116 } else if (N.getOpcode() == ISD::OR) {
1186 if (N.getOpcode() == ISD::ADD) {
1204 ISD::MemIndexedMode &AM,
1247 AM = ISD::PRE_INC;
1268 LD->getExtensionType() == ISD::SEXTLOAD &&
1273 AM = ISD::PRE_INC;
1323 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1328 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1515 if (C->isNullValue() && CC == ISD::SETEQ) {
1520 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1523 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1524 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1526 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1541 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1543 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1563 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1570 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1573 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1574 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1577 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1582 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1586 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1591 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1594 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1610 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1613 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1619 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1624 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1628 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1639 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1642 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1646 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1789 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1798 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1806 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1819 ISD::ArgFlagsTy &ArgFlags,
1827 ISD::ArgFlagsTy &ArgFlags,
1854 ISD::ArgFlagsTy &ArgFlags,
1891 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1904 const SmallVectorImpl<ISD::InputArg>
1926 const SmallVectorImpl<ISD::InputArg>
2109 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2129 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2134 Chain = DAG.getNode(ISD::TokenFactor, dl,
2143 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2147 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2150 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2153 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2186 const SmallVectorImpl<ISD::InputArg>
2238 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2460 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2465 Chain = DAG.getNode(ISD::TokenFactor, dl,
2475 const SmallVectorImpl<ISD::InputArg>
2532 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2583 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2811 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2816 Chain = DAG.getNode(ISD::TokenFactor, dl,
2829 const SmallVectorImpl<ISD::OutputArg>
2848 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2914 const SmallVectorImpl<ISD::InputArg> &Ins,
2928 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3087 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3112 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3137 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3261 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3337 const SmallVectorImpl<ISD::InputArg> &Ins,
3360 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3363 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3365 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3368 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3370 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3389 const SmallVectorImpl<ISD::InputArg> &Ins,
3419 assert(((Callee.getOpcode() == ISD::Register &&
3421 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3422 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3481 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3483 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3514 const SmallVectorImpl<ISD::OutputArg> &Outs,
3516 const SmallVectorImpl<ISD::InputArg> &Ins,
3558 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3629 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3644 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3678 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3692 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3730 ISD::ArgFlagsTy Flags,
3749 const SmallVectorImpl<ISD::OutputArg> &Outs,
3751 const SmallVectorImpl<ISD::InputArg> &Ins,
3835 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3843 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3848 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3872 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3886 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3922 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3943 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3984 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4008 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4034 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4050 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4076 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4090 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4121 const SmallVectorImpl<ISD::OutputArg> &Outs,
4123 const SmallVectorImpl<ISD::InputArg> &Ins,
4217 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4225 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4230 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4244 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4254 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4274 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4323 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4366 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4382 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4435 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4469 const SmallVectorImpl<ISD::OutputArg> &Outs,
4480 const SmallVectorImpl<ISD::OutputArg> &Outs,
4503 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4506 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4509 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4621 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4661 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4675 case ISD::SETNE:
4677 case ISD::SETEQ:
4679 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4682 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4684 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4685 case ISD::SETULT:
4686 case ISD::SETLT:
4688 case ISD::SETOGE:
4689 case ISD::SETGE:
4691 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4693 case ISD::SETUGT:
4694 case ISD::SETGT:
4696 case ISD::SETOLE:
4697 case ISD::SETLE:
4699 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4701 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4707 case ISD::SETNE:
4709 case ISD::SETEQ:
4710 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4712 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4715 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4717 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4718 case ISD::SETULT:
4719 case ISD::SETLT:
4720 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4722 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4724 case ISD::SETOGE:
4725 case ISD::SETGE:
4726 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4728 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4730 case ISD::SETUGT:
4731 case ISD::SETGT:
4732 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4734 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4736 case ISD::SETOLE:
4737 case ISD::SETLE:
4738 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4740 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4752 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4758 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4764 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4766 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4774 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4796 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4812 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4818 (Op.getOpcode() == ISD::UINT_TO_FP ?
4820 (Op.getOpcode() == ISD::UINT_TO_FP ?
4847 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4849 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4851 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4852 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4863 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4865 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4868 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4870 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4873 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4877 FP = DAG.getNode(ISD::FP_ROUND, dl,
4907 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4918 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4935 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4981 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4987 DAG.getNode(ISD::AND, dl, MVT::i32,
4990 DAG.getNode(ISD::SRL, dl, MVT::i32,
4991 DAG.getNode(ISD::AND, dl, MVT::i32,
4992 DAG.getNode(ISD::XOR, dl, MVT::i32,
4998 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5001 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5019 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5023 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5024 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5027 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5048 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5052 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5053 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5056 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5076 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5080 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5081 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5086 Tmp4, Tmp6, ISD::SETLE);
5117 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5119 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5128 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5138 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5148 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5158 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5159 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5165 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5198 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5199 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5243 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5244 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5270 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5281 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5292 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5304 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5398 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5399 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5401 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5419 if (V2.getOpcode() == ISD::UNDEF) {
5506 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5522 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5588 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5626 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5629 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5634 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5669 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5670 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5671 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5683 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5697 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5702 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5721 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5722 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5723 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5724 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5725 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5726 case ISD::SETCC: return LowerSETCC(Op, DAG);
5727 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5728 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5729 case ISD::VASTART:
5732 case ISD::VAARG:
5735 case ISD::VACOPY:
5738 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5739 case ISD::DYNAMIC_STACKALLOC:
5742 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5743 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5745 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5746 case ISD::FP_TO_UINT:
5747 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5749 case ISD::UINT_TO_FP:
5750 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5751 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5754 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5755 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5756 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5759 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5760 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5761 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5762 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5763 case ISD::MUL: return LowerMUL(Op, DAG);
5766 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5769 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5770 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5782 case ISD::INTRINSIC_W_CHAIN: {
5798 case ISD::VAARG: {
5813 case ISD::FP_ROUND_INREG: {
5816 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5819 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5828 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5832 case ISD::FP_TO_SINT:
6770 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6779 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6782 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6785 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6788 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6832 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6842 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6845 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6850 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6853 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6856 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6859 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6880 if (Loc.getOpcode() == ISD::FrameIndex) {
6881 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6936 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6970 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7004 case ISD::FDIV: {
7008 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7013 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7016 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7017 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7023 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7026 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7029 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7030 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7036 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7040 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7048 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7054 case ISD::FSQRT: {
7070 case ISD::SINT_TO_FP:
7072 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7080 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7089 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7101 case ISD::STORE:
7105 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7110 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7131 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7141 ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7154 case ISD::LOAD: {
7159 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7223 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7231 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7235 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7238 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7244 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7281 case ISD::INTRINSIC_WO_CHAIN:
7284 N->getOperand(1)->getOpcode() == ISD::ADD) {
7293 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7305 case ISD::BSWAP:
7307 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7330 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7396 case ISD::BR_CC: {
7401 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7406 if (LHS.getOpcode() == ISD::AND &&
7407 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7415 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7419 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7423 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7424 (CC == ISD::SETNE && !Val);
7439 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7440 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7448 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7451 return DAG.getNode(ISD::BR, dl, MVT::Other,
7455 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7514 case ISD::INTRINSIC_WO_CHAIN: {
7785 DAG.getNode(ISD::ADD, dl, getPointerTy(),
