Lines Matching refs:MVT
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
158 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
160 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
167 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
168 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
171 setOperationAction(ISD::FRINT, MVT::f64, Legal);
172 setOperationAction(ISD::FRINT, MVT::f32, Legal);
177 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
181 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
183 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
184 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
187 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
188 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
190 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
191 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
195 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
196 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
199 setOperationAction(ISD::SELECT, MVT::i32, Expand);
200 setOperationAction(ISD::SELECT, MVT::i64, Expand);
201 setOperationAction(ISD::SELECT, MVT::f32, Expand);
202 setOperationAction(ISD::SELECT, MVT::f64, Expand);
205 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
206 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
209 setOperationAction(ISD::SETCC, MVT::i32, Custom);
212 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
214 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
217 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
220 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
221 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
223 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
224 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
225 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
226 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
237 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
238 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
244 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
245 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
246 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
247 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
248 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
249 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
250 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
251 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
254 setOperationAction(ISD::TRAP, MVT::Other, Legal);
257 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
258 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
261 setOperationAction(ISD::VASTART , MVT::Other, Custom);
266 setOperationAction(ISD::VAARG, MVT::i1, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i8, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::i16, Promote);
271 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
272 setOperationAction(ISD::VAARG, MVT::i32, Promote);
273 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
274 setOperationAction(ISD::VAARG, MVT::Other, Expand);
277 setOperationAction(ISD::VAARG, MVT::Other, Custom);
278 setOperationAction(ISD::VAARG, MVT::i64, Custom);
281 setOperationAction(ISD::VAARG, MVT::Other, Expand);
285 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
287 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
290 setOperationAction(ISD::VAEND , MVT::Other, Expand);
291 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
292 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
293 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
294 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
297 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
300 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
303 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
311 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
318 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
319 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
320 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
321 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
324 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
327 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
330 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
336 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
337 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
338 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
339 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
342 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
343 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
345 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
350 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
352 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
354 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
355 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
356 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
359 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
360 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
361 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
367 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
368 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
369 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
377 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
381 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
383 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
385 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
387 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
389 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
391 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
434 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
435 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
436 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
446 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
448 setOperationAction(ISD::AND , MVT::v4i32, Legal);
449 setOperationAction(ISD::OR , MVT::v4i32, Legal);
450 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
451 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
452 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
453 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
454 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
455 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
456 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
457 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
458 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
459 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
460 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
461 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
463 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
464 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
465 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
466 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
468 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
472 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
473 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
476 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
477 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
478 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
480 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
481 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
483 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
485 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
486 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
489 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
491 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
494 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
496 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
497 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
501 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
502 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
505 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
506 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
507 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
508 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
669 return MVT::i32;
735 assert(N->getValueType(0) == MVT::v16i8 &&
773 assert(N->getValueType(0) == MVT::v16i8 &&
809 assert(N->getValueType(0) == MVT::v16i8 &&
906 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
909 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
913 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
916 return DAG.getTargetConstant(Val, MVT::i32);
938 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
967 return DAG.getTargetConstant(MaskVal, MVT::i32);
984 if (N->getValueType(0) == MVT::i32)
1048 if (VT != MVT::i64)
1148 if ((CN->getValueType(0) == MVT::i32 ||
1154 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1156 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1157 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1252 if (VT != MVT::i64) {
1267 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1341 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1342 DAG.getRegister(PPC::X2, MVT::i64));
1362 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1363 DAG.getRegister(PPC::X2, MVT::i64));
1403 is64bit ? MVT::i64 : MVT::i32);
1415 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1425 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1436 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1448 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1459 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1485 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1486 DAG.getRegister(PPC::X2, MVT::i64));
1518 if (VT.bitsLT(MVT::i32)) {
1519 VT = MVT::i32;
1525 DAG.getConstant(Log2b, MVT::i32));
1526 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1563 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1564 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1568 if (VT == MVT::i64) {
1570 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1571 DAG.getConstant(1, MVT::i32));
1572 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1573 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1574 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1575 DAG.getConstant(1, MVT::i32));
1577 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1583 DAG.getConstant(1, MVT::i32));
1586 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1587 FprPtr, MachinePointerInfo(SV), MVT::i8,
1592 DAG.getConstant(8, MVT::i32));
1595 DAG.getConstant(4, MVT::i32));
1598 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1603 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1609 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1610 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1613 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1616 MVT::i32));
1625 DAG.getConstant(32, MVT::i32));
1628 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1630 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1631 MVT::i32));
1636 MVT::i8, false, false, 0);
1644 MVT::i32));
1646 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1652 MVT::i32, false, false, 0);
1666 DAG.getConstant(12, MVT::i32), 8, false, true,
1684 bool isPPC64 = (PtrVT == MVT::i64);
1697 isPPC64 ? MVT::i64 : MVT::i32);
1761 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1762 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1787 MVT::i8, false, false, 0);
1795 MachinePointerInfo(SV, nextOffset), MVT::i8,
1817 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1824 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1825 MVT &LocVT,
1851 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1852 MVT &LocVT,
1991 case MVT::i32:
1994 case MVT::f32:
1997 case MVT::f64:
2000 case MVT::v16i8:
2001 case MVT::v8i16:
2002 case MVT::v4i32:
2003 case MVT::v4f32:
2085 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2122 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2127 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2135 MVT::Other, &MemOps[0], MemOps.size());
2141 // value to MVT::i64 and then truncate to the correct register size.
2147 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2150 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2153 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2245 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2246 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2294 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2295 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2348 case MVT::i32:
2349 case MVT::i64:
2352 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2354 if (ObjectVT == MVT::i32)
2356 // value to MVT::i64 and then truncate to the correct register size.
2367 case MVT::f32:
2368 case MVT::f64:
2377 if (ObjectVT == MVT::f32)
2391 case MVT::v4f32:
2392 case MVT::v4i32:
2393 case MVT::v8i16:
2394 case MVT::v16i8:
2466 MVT::Other, &MemOps[0], MemOps.size());
2486 bool isPPC64 = PtrVT == MVT::i64;
2545 case MVT::i32:
2546 case MVT::f32:
2549 case MVT::i64: // PPC64
2550 case MVT::f64:
2552 // Does MVT::i64 apply?
2555 case MVT::v4f32:
2556 case MVT::v4i32:
2557 case MVT::v8i16:
2558 case MVT::v16i8:
2590 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2591 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2627 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2669 case MVT::i32:
2673 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2684 case MVT::i64: // PPC64
2687 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2689 if (ObjectVT == MVT::i32)
2691 // value to MVT::i64 and then truncate to the correct register size.
2703 case MVT::f32:
2704 case MVT::f64:
2715 if (ObjectVT == MVT::f32)
2729 case MVT::v4f32:
2730 case MVT::v4i32:
2731 case MVT::v8i16:
2732 case MVT::v16i8:
2817 MVT::Other, &MemOps[0], MemOps.size());
2851 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2852 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
3009 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3040 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3061 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3089 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3109 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3111 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3137 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3161 NodeTys.push_back(MVT::Other); // Returns a chain
3162 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3251 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3261 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3278 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3294 NodeTys.push_back(MVT::Other);
3295 NodeTys.push_back(MVT::Glue);
3314 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3399 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3426 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3461 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3557 MVT ArgVT = Outs[i].VT;
3616 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3692 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3707 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3806 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3846 if (Arg.getValueType() == MVT::i32) {
3849 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3870 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3961 case MVT::i32:
3962 case MVT::i64:
3972 case MVT::f32:
3973 case MVT::f64:
3982 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
4006 if (Arg.getValueType() == MVT::f32) {
4017 case MVT::v4f32:
4018 case MVT::v4i32:
4019 case MVT::v8i16:
4020 case MVT::v16i8:
4040 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4076 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4087 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4130 bool isPPC64 = PtrVT == MVT::i64;
4180 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4182 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4228 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4231 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4242 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4292 case MVT::i32:
4293 case MVT::i64:
4303 case MVT::f32:
4304 case MVT::f64:
4321 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4336 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4347 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4349 case MVT::v4f32:
4350 case MVT::v4i32:
4351 case MVT::v8i16:
4352 case MVT::v16i8:
4372 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4420 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4421 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4435 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4524 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4627 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4635 DAG.getVTList(MVT::i32, MVT::Other),
4642 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4678 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4679 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4681 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4682 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4684 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4690 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4691 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4698 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4699 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4701 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4711 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4712 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4714 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4715 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4717 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4721 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4722 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4727 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4728 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4733 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4734 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4739 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4740 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4751 if (Src.getValueType() == MVT::f32)
4752 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4757 case MVT::i32:
4761 dl, MVT::f64, Src);
4763 case MVT::i64:
4768 dl, MVT::f64, Src);
4773 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4775 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4787 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4788 MVT::i32, MMO);
4795 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4809 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4817 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4822 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4823 MVT::f32 : MVT::f64;
4825 if (Op.getOperand(0).getValueType() == MVT::i64) {
4837 if (Op.getValueType() == MVT::f32 &&
4847 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4848 SINT, DAG.getConstant(2047, MVT::i64));
4849 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4850 Round, DAG.getConstant(2047, MVT::i64));
4851 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4852 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4853 Round, DAG.getConstant(-2048, MVT::i64));
4863 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4864 SINT, DAG.getConstant(53, MVT::i32));
4865 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4866 Cond, DAG.getConstant(1, MVT::i64));
4867 Cond = DAG.getSetCC(dl, MVT::i32,
4868 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4870 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4873 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4876 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4878 MVT::f32, FP, DAG.getIntPtrConstant(0));
4882 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4901 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4909 dl, DAG.getVTList(MVT::f64, MVT::Other),
4910 Ops, 2, MVT::i32, MMO);
4918 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4927 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4934 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4935 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4968 MVT::f64, // return register
4969 MVT::Glue // unused in this context
4982 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4987 DAG.getNode(ISD::AND, dl, MVT::i32,
4988 CWD, DAG.getConstant(3, MVT::i32));
4990 DAG.getNode(ISD::SRL, dl, MVT::i32,
4991 DAG.getNode(ISD::AND, dl, MVT::i32,
4992 DAG.getNode(ISD::XOR, dl, MVT::i32,
4993 CWD, DAG.getConstant(3, MVT::i32)),
4994 DAG.getConstant(3, MVT::i32)),
4995 DAG.getConstant(1, MVT::i32));
4998 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5102 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5105 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5114 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5126 EVT DestVT = MVT::Other) {
5127 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5129 DAG.getConstant(IID, MVT::i32), Op);
5136 EVT DestVT = MVT::Other) {
5137 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5139 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5146 SDLoc dl, EVT DestVT = MVT::Other) {
5147 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5149 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5158 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5159 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5164 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5196 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5197 SDValue Z = DAG.getConstant(0, MVT::i32);
5198 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5224 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5226 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5227 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5236 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5243 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5264 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5275 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5286 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5298 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5309 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5314 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5319 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5398 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5399 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5400 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5519 MVT::i32));
5522 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5587 DAG.getConstant(CompareOpc, MVT::i32));
5595 DAG.getConstant(CompareOpc, MVT::i32)
5597 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5602 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5603 DAG.getRegister(PPC::CR6, MVT::i32),
5626 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5627 DAG.getConstant(8-(3-BitNo), MVT::i32));
5629 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5630 DAG.getConstant(1, MVT::i32));
5634 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5635 DAG.getConstant(1, MVT::i32));
5659 if (Op.getValueType() == MVT::v4i32) {
5662 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5663 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5669 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5670 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5671 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5676 LHS, RHS, DAG, dl, MVT::v4i32);
5679 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5683 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5684 } else if (Op.getValueType() == MVT::v8i16) {
5687 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5691 } else if (Op.getValueType() == MVT::v16i8) {
5696 LHS, RHS, DAG, dl, MVT::v8i16);
5697 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5701 LHS, RHS, DAG, dl, MVT::v8i16);
5702 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5710 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5787 assert(N->getValueType(0) == MVT::i1 &&
5790 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5805 if (VT == MVT::i64) {
5814 assert(N->getValueType(0) == MVT::ppcf128);
5815 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5817 MVT::f64, N->getOperand(0),
5820 MVT::f64, N->getOperand(0),
5824 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5828 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5834 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6057 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6061 MVT PVT = getPointerTy();
6062 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6199 MVT PVT = getPointerTy();
6200 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6204 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6207 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6208 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6209 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6223 if (PVT == MVT::i64) {
6235 if (PVT == MVT::i64) {
6247 if (PVT == MVT::i64) {
6259 if (PVT == MVT::i64) {
6271 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6281 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6282 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6743 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6744 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6745 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6759 if (VT.getScalarType() == MVT::f64)
6805 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6806 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6807 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6821 if (VT.getScalarType() == MVT::f64)
7076 if (N->getOperand(0).getValueType() == MVT::i64 &&
7077 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7079 if (Val.getValueType() == MVT::f32) {
7080 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7084 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7086 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7088 if (N->getValueType(0) == MVT::f32) {
7089 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7094 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7106 N->getOperand(1).getValueType() == MVT::i32 &&
7107 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7109 if (Val.getValueType() == MVT::f32) {
7110 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7113 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7122 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7133 (N->getOperand(1).getValueType() == MVT::i32 ||
7134 N->getOperand(1).getValueType() == MVT::i16 ||
7137 N->getOperand(1).getValueType() == MVT::i64))) {
7140 if (BSwapOp.getValueType() == MVT::i16)
7141 MVT::i32, BSwapOp);
7148 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7191 DAG, dl, MVT::v16i8);
7231 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7234 if (BaseLoad.getValueType() != MVT::v4i32)
7235 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7237 if (ExtraLoad.getValueType() != MVT::v4i32)
7238 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7243 if (VT != MVT::v4i32)
7309 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7312 N->getValueType(0) == MVT::i64))) {
7323 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7324 MVT::i64 : MVT::i32, MVT::Other),
7329 if (N->getValueType(0) == MVT::i16)
7330 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7432 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7451 return DAG.getNode(ISD::BR, dl, MVT::Other,
7461 DAG.getConstant(CompareOpc, MVT::i32)
7463 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7484 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7485 DAG.getConstant(CompOpc, MVT::i32),
7486 DAG.getRegister(PPC::CR6, MVT::i32),
7510 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7610 MVT VT) const {
7615 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7619 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7623 if (VT == MVT::f32 || VT == MVT::i32)
7625 if (VT == MVT::f64 || VT == MVT::i64)
7644 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7783 isPPC64? MVT::i64 : MVT::i32);
7802 bool isPPC64 = PtrVT == MVT::i64;
7849 return MVT::i64;
7851 return MVT::i32;
7872 if (VT == MVT::ppcf128)
7888 case MVT::f32:
7889 case MVT::f64:
