Lines Matching refs:STD
1081 /// suitable for STD and friends, i.e. multiples of 4.
1245 std::swap(Base, Offset);
1713 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2051 std::max(MinReservedArea,
2172 std::max(MinReservedArea,
2239 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2407 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2584 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2745 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2876 NumBytes = std::max(NumBytes,
3153 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3154 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3384 SmallVector<std::pair<unsigned, SDValue>, 8>
3391 std::vector<EVT> NodeTys;
3618 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3670 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3829 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3876 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3932 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3949 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3964 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3975 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3998 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4044 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4055 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4064 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4096 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4211 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4248 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4280 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4295 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4306 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4319 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4328 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4376 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4387 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4396 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4445 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4676 std::swap(TV, FV);
4687 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4695 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4708 std::swap(TV, FV);
4921 // STD the extended value into the stack slot.
6115 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6132 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6160 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7541 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7608 std::pair<unsigned, const TargetRegisterClass*>
7609 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7616 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7617 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7620 return std::make_pair(0U, &PPC::G8RCRegClass);
7621 return std::make_pair(0U, &PPC::GPRCRegClass);
7624 return std::make_pair(0U, &PPC::F4RCRegClass);
7626 return std::make_pair(0U, &PPC::F8RCRegClass);
7629 return std::make_pair(0U, &PPC::VRRCRegClass);
7631 return std::make_pair(0U, &PPC::CRRCRegClass);
7635 std::pair<unsigned, const TargetRegisterClass*> R =
7647 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7659 std::string &Constraint,
7660 std::vector<SDValue>&Ops,
