Lines Matching refs:v4f32
458 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
459 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
460 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
461 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
463 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
468 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
469 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
472 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
473 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
480 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
486 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
489 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
491 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
494 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
496 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
497 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
2003 case MVT::v4f32:
2245 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2391 case MVT::v4f32:
2555 case MVT::v4f32:
2590 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2729 case MVT::v4f32:
2851 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
4017 case MVT::v4f32:
4040 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4349 case MVT::v4f32:
4372 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4420 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
6745 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6807 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
