Lines Matching refs:v8i16
465 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
477 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
484 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
2001 case MVT::v8i16:
2246 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2393 case MVT::v8i16:
2557 case MVT::v8i16:
2591 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2731 case MVT::v8i16:
2852 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
4019 case MVT::v8i16:
4351 case MVT::v8i16:
4421 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5102 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5226 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5668 // Shrinkify inputs to v8i16.
5669 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5670 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5671 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5684 } else if (Op.getValueType() == MVT::v8i16) {
5687 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5696 LHS, RHS, DAG, dl, MVT::v8i16);
5701 LHS, RHS, DAG, dl, MVT::v8i16);
