Lines Matching full:pseudo
554 // pseudo-instructions.
572 // pseudo-instructions.
833 // Pseudo-instructions:
837 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
839 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
843 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
848 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
859 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
863 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
867 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
870 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
873 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
881 def SPILL_CR : Pseudo<(outs), (ins crrc:$cond, memri:$F),
887 def RESTORE_CR : Pseudo<(outs crrc:$cond), (ins memri:$F),
904 def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
1057 def TCRETURNdi :Pseudo< (outs),
1064 def TCRETURNai :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
1069 def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset),
1097 def EH_SjLj_SetJmp32 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
1102 def EH_SjLj_LongJmp32 : Pseudo<(outs), (ins memr:$buf),
1109 def EH_SjLj_Setup : Pseudo<(outs), (ins directbrtarget:$dst),
1151 def ATOMIC_LOAD_ADD_I8 : Pseudo<
1154 def ATOMIC_LOAD_SUB_I8 : Pseudo<
1157 def ATOMIC_LOAD_AND_I8 : Pseudo<
1160 def ATOMIC_LOAD_OR_I8 : Pseudo<
1163 def ATOMIC_LOAD_XOR_I8 : Pseudo<
1166 def ATOMIC_LOAD_NAND_I8 : Pseudo<
1169 def ATOMIC_LOAD_ADD_I16 : Pseudo<
1172 def ATOMIC_LOAD_SUB_I16 : Pseudo<
1175 def ATOMIC_LOAD_AND_I16 : Pseudo<
1178 def ATOMIC_LOAD_OR_I16 : Pseudo<
1181 def ATOMIC_LOAD_XOR_I16 : Pseudo<
1184 def ATOMIC_LOAD_NAND_I16 : Pseudo<
1187 def ATOMIC_LOAD_ADD_I32 : Pseudo<
1190 def ATOMIC_LOAD_SUB_I32 : Pseudo<
1193 def ATOMIC_LOAD_AND_I32 : Pseudo<
1196 def ATOMIC_LOAD_OR_I32 : Pseudo<
1199 def ATOMIC_LOAD_XOR_I32 : Pseudo<
1202 def ATOMIC_LOAD_NAND_I32 : Pseudo<
1206 def ATOMIC_CMP_SWAP_I8 : Pseudo<
1209 def ATOMIC_CMP_SWAP_I16 : Pseudo<
1212 def ATOMIC_CMP_SWAP_I32 : Pseudo<
1216 def ATOMIC_SWAP_I8 : Pseudo<
1219 def ATOMIC_SWAP_I16 : Pseudo<
1222 def ATOMIC_SWAP_I32 : Pseudo<
1702 def FRINDrint : Pseudo<(outs f8rc:$frD), (ins f8rc:$frB),
1704 def FRINSrint : Pseudo<(outs f4rc:$frD), (ins f4rc:$frB),
1741 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
1912 def SPILL_VRSAVE : Pseudo<(outs), (ins VRSAVERC:$vrsave, memri:$F),
1918 def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F),
1939 // Pseudo instruction to perform FADD in round-to-zero mode.
1941 def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
1945 // The above pseudo gets expanded to make use of the following instructions
2307 // Pseudo-instructions for alternate assembly syntax (never used by codegen).
