Lines Matching refs:ISD
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
76 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
79 setOperationAction(ISD::LOAD, MVT::f64, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
82 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Expand);
83 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Expand);
85 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
86 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
88 setOperationAction(ISD::MUL, MVT::i64, Expand);
90 setOperationAction(ISD::UDIV, MVT::i32, Expand);
91 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
92 setOperationAction(ISD::UREM, MVT::i32, Expand);
93 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
94 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
105 setOperationAction(ISD::ADD, VT, Expand);
106 setOperationAction(ISD::AND, VT, Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
109 setOperationAction(ISD::MUL, VT, Expand);
110 setOperationAction(ISD::OR, VT, Expand);
111 setOperationAction(ISD::SHL, VT, Expand);
112 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
113 setOperationAction(ISD::SRL, VT, Expand);
114 setOperationAction(ISD::SRA, VT, Expand);
115 setOperationAction(ISD::SUB, VT, Expand);
116 setOperationAction(ISD::UDIV, VT, Expand);
117 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
118 setOperationAction(ISD::UREM, VT, Expand);
119 setOperationAction(ISD::VSELECT, VT, Expand);
120 setOperationAction(ISD::XOR, VT, Expand);
152 const SmallVectorImpl<ISD::InputArg> &Ins) const {
161 const SmallVectorImpl<ISD::OutputArg> &Outs,
180 case ISD::SDIV: return LowerSDIV(Op, DAG);
181 case ISD::SREM: return LowerSREM(Op, DAG);
182 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
183 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
185 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
186 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
222 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
246 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
256 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
268 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
271 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
273 return DAG.getNode(ISD::FADD, DL, VT,
274 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
295 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
297 case ISD::SETOEQ:
298 case ISD::SETONE:
299 case ISD::SETUNE:
300 case ISD::SETNE:
301 case ISD::SETUEQ:
302 case ISD::SETEQ:
303 case ISD::SETFALSE:
304 case ISD::SETFALSE2:
305 case ISD::SETTRUE:
306 case ISD::SETTRUE2:
307 case ISD::SETUO:
308 case ISD::SETO:
310 case ISD::SETULE:
311 case ISD::SETULT:
312 case ISD::SETOLE:
313 case ISD::SETOLT:
314 case ISD::SETLE:
315 case ISD::SETLT: {
321 case ISD::SETGT:
322 case ISD::SETGE:
323 case ISD::SETUGE:
324 case ISD::SETOGE:
325 case ISD::SETUGT:
326 case ISD::SETOGT: {
332 case ISD::SETCC_INVALID:
355 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
358 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
361 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
367 ISD::SETEQ);
370 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
373 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
376 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
381 ISD::SETEQ);
383 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
386 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
389 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
395 ISD::SETGE);
401 ISD::SETGE);
403 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
409 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
413 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
418 Quotient, Quotient_A_One, ISD::SETEQ);
422 Quotient_S_One, Div, ISD::SETEQ);
427 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
430 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
434 Remainder, Remainder_S_Den, ISD::SETEQ);
438 Remainder_A_Den, Rem, ISD::SETEQ);
