Lines Matching defs:AMDGPUInstrInfo
1 //===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===//
16 #include "AMDGPUInstrInfo.h"
30 AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
33 const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
37 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
44 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
50 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
56 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
62 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
67 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
72 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
80 AMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
86 bool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter,
103 AMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
113 AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
122 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
130 AMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
138 AMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
144 AMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
153 AMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
160 AMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
167 bool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
179 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
184 void AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB,
189 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {
194 AMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
201 bool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI,
207 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {
213 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
218 bool AMDGPUInstrInfo::isRegisterStore(const MachineInstr &MI) const {
222 bool AMDGPUInstrInfo::isRegisterLoad(const MachineInstr &MI) const {
227 void AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
