Lines Matching refs:AMDGPU
17 #include "AMDGPU.h"
74 case AMDGPU::PRED_X: {
82 AMDGPU::ZERO); // src1
85 TII->setImmOperand(PredSet, AMDGPU::OpName::update_exec_mask, 1);
87 TII->setImmOperand(PredSet, AMDGPU::OpName::update_pred, 1);
93 case AMDGPU::INTERP_PAIR_XY: {
95 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
104 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
106 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
122 case AMDGPU::INTERP_PAIR_ZW: {
124 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
131 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
135 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
151 case AMDGPU::INTERP_VEC_LOAD: {
154 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
159 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
171 case AMDGPU::DOT_4: {
181 AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
199 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1))
246 TII->getOperandIdx(MI, AMDGPU::OpName::dst)).getReg();
248 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
253 int Src1Idx = TII->getOperandIdx(MI, AMDGPU::OpName::src1);
281 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
290 case AMDGPU::CUBE_r600_pseudo:
291 Opcode = AMDGPU::CUBE_r600_real;
293 case AMDGPU::CUBE_eg_pseudo:
294 Opcode = AMDGPU::CUBE_eg_real;
