Lines Matching refs:BUILD_VECTOR
1147 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
1227 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1285 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1316 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1322 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1347 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1354 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1425 // insert_vector_elt (build_vector elt0, ?, eltN), NewEltIdx, idx
1426 // => build_vector elt0, ?, NewEltIdx, ?, eltN
1439 // If we can't generate a legal BUILD_VECTOR, exit
1440 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1448 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1449 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1452 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1464 // All the operands of BUILD_VECTOR must have the same type;
1475 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1479 // Extract_vec (Build_vector) generated by custom lowering
1483 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1490 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1539 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1558 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
