Lines Matching refs:ISD
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
42 setOperationAction(ISD::FADD, MVT::v2f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
44 setOperationAction(ISD::FMUL, MVT::v2f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
46 setOperationAction(ISD::FDIV, MVT::v2f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
48 setOperationAction(ISD::FSUB, MVT::v2f32, Expand);
50 setOperationAction(ISD::FCOS, MVT::f32, Custom);
51 setOperationAction(ISD::FSIN, MVT::f32, Custom);
53 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
54 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
56 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
57 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
59 setOperationAction(ISD::FSUB, MVT::f32, Expand);
61 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
62 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
63 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
68 setOperationAction(ISD::SETCC, MVT::i32, Expand);
69 setOperationAction(ISD::SETCC, MVT::f32, Expand);
70 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
72 setOperationAction(ISD::SELECT, MVT::i32, Custom);
73 setOperationAction(ISD::SELECT, MVT::f32, Custom);
76 setOperationAction(ISD::LOAD, MVT::i32, Custom);
77 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
78 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
79 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
83 setOperationAction(ISD::STORE, MVT::i8, Custom);
84 setOperationAction(ISD::STORE, MVT::i32, Custom);
85 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
86 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
92 setTargetDAGCombine(ISD::FP_ROUND);
93 setTargetDAGCombine(ISD::FP_TO_SINT);
94 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
95 setTargetDAGCombine(ISD::SELECT_CC);
96 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
98 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
486 case ISD::FCOS:
487 case ISD::FSIN: return LowerTrig(Op, DAG);
488 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
489 case ISD::SELECT: return LowerSELECT(Op, DAG);
490 case ISD::STORE: return LowerSTORE(Op, DAG);
491 case ISD::LOAD: return LowerLOAD(Op, DAG);
492 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
493 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
494 case ISD::INTRINSIC_VOID: {
523 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
526 case ISD::INTRINSIC_WO_CHAIN: {
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
660 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
662 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
664 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
708 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
720 case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), DAG));
722 case ISD::LOAD: {
731 case ISD::STORE:
744 DAG.getNode(ISD::FADD, SDLoc(Op), VT,
745 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
750 case ISD::FCOS:
753 case ISD::FSIN:
760 DAG.getNode(ISD::FADD, SDLoc(Op), VT, FractPart,
765 return DAG.getNode(ISD::FMUL, SDLoc(Op), VT, TrigVal,
771 ISD::SETCC,
775 DAG.getCondCode(ISD::SETNE)
846 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
848 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
854 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
869 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
875 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
876 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
879 CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
883 case ISD::SETONE:
884 case ISD::SETUNE:
885 case ISD::SETNE:
886 case ISD::SETULE:
887 case ISD::SETULT:
888 case ISD::SETOLE:
889 case ISD::SETOLT:
890 case ISD::SETLE:
891 case ISD::SETLT:
892 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
900 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
904 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode);
931 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
933 return DAG.getNode(ISD::SELECT_CC, DL, VT,
936 DAG.getCondCode(ISD::SETNE));
940 return DAG.getNode(ISD::SELECT_CC,
947 DAG.getCondCode(ISD::SETNE));
972 return DAG.getNode(ISD::SRL, SDLoc(Ptr), Ptr.getValueType(), Ptr,
1016 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
1053 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1055 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT,
1062 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1065 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1137 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1147 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, Slots, NumElements);
1151 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1158 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1170 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
1176 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1181 SDValue NewLoad = DAG.getExtLoad(ISD::EXTLOAD, DL, VT, Chain, Ptr,
1186 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, NewLoad, ShiftAmount);
1187 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Shl, ShiftAmount);
1216 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1227 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads, 4);
1249 const SmallVectorImpl<ISD::InputArg> &Ins,
1285 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1305 if (NewBldVec[i].getOpcode() == ISD::UNDEF)
1316 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1322 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR);
1335 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1347 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry),
1354 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR);
1387 case ISD::FP_ROUND: {
1389 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1390 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
1401 case ISD::FP_TO_SINT: {
1403 if (FNeg.getOpcode() != ISD::FNEG) {
1407 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1415 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1427 case ISD::INSERT_VECTOR_ELT: {
1434 if (InVal.getOpcode() == ISD::UNDEF)
1440 if (!isOperationLegal(ISD::BUILD_VECTOR, VT))
1452 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1455 } else if (InVec.getOpcode() == ISD::UNDEF) {
1469 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
1470 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
1475 return DAG.getNode(ISD::BUILD_VECTOR, dl,
1481 case ISD::EXTRACT_VECTOR_ELT: {
1483 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1489 if (Arg.getOpcode() == ISD::BITCAST &&
1490 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
1493 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
1499 case ISD::SELECT_CC: {
1506 if (LHS.getOpcode() != ISD::SELECT_CC) {
1513 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1523 case ISD::SETNE: return LHS;
1524 case ISD::SETEQ: {
1525 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get();
1526 LHSCC = ISD::getSetCCInverse(LHSCC,
1539 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1558 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
