Lines Matching refs:MVT
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
37 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
42 setOperationAction(ISD::FADD, MVT::v2f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
44 setOperationAction(ISD::FMUL, MVT::v2f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
46 setOperationAction(ISD::FDIV, MVT::v2f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
48 setOperationAction(ISD::FSUB, MVT::v2f32, Expand);
50 setOperationAction(ISD::FCOS, MVT::f32, Custom);
51 setOperationAction(ISD::FSIN, MVT::f32, Custom);
53 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
54 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
56 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
57 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
59 setOperationAction(ISD::FSUB, MVT::f32, Expand);
61 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
62 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
63 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
68 setOperationAction(ISD::SETCC, MVT::i32, Expand);
69 setOperationAction(ISD::SETCC, MVT::f32, Expand);
70 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
72 setOperationAction(ISD::SELECT, MVT::i32, Custom);
73 setOperationAction(ISD::SELECT, MVT::f32, Custom);
76 setOperationAction(ISD::LOAD, MVT::i32, Custom);
77 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
78 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
79 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
81 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
82 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
83 setOperationAction(ISD::STORE, MVT::i8, Custom);
84 setOperationAction(ISD::STORE, MVT::i32, Custom);
85 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
86 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::i32, Custom);
89 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
98 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
511 DAG.getConstant(0, MVT::i32), // SWZ_X
512 DAG.getConstant(1, MVT::i32), // SWZ_Y
513 DAG.getConstant(2, MVT::i32), // SWZ_Z
514 DAG.getConstant(3, MVT::i32) // SWZ_W
552 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
555 DL, MVT::f32, SDValue(interp, 0));
565 SDLoc(DAG.getEntryNode()), RegisterI, MVT::f32);
567 SDLoc(DAG.getEntryNode()), RegisterJ, MVT::f32);
571 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
575 MVT::f32, MVT::f32, DAG.getTargetConstant(slot / 4 , MVT::i32),
626 DAG.getConstant(TextureOp, MVT::i32),
628 DAG.getConstant(0, MVT::i32),
629 DAG.getConstant(1, MVT::i32),
630 DAG.getConstant(2, MVT::i32),
631 DAG.getConstant(3, MVT::i32),
635 DAG.getConstant(0, MVT::i32),
636 DAG.getConstant(1, MVT::i32),
637 DAG.getConstant(2, MVT::i32),
638 DAG.getConstant(3, MVT::i32),
646 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
651 DAG.getConstant(0, MVT::i32)),
652 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
653 DAG.getConstant(0, MVT::i32)),
654 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
655 DAG.getConstant(1, MVT::i32)),
656 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
657 DAG.getConstant(1, MVT::i32)),
658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
659 DAG.getConstant(2, MVT::i32)),
660 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
661 DAG.getConstant(2, MVT::i32)),
662 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
663 DAG.getConstant(3, MVT::i32)),
664 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
665 DAG.getConstant(3, MVT::i32))
667 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args, 8);
746 DAG.getConstantFP(0.15915494309, MVT::f32)),
747 DAG.getConstantFP(0.5, MVT::f32)));
761 DAG.getConstantFP(-0.5, MVT::f32)));
766 DAG.getConstantFP(3.14159265359, MVT::f32));
773 MVT::i1,
774 Op, DAG.getConstantFP(0.0f, MVT::f32),
790 DAG.getConstant(ByteOffset, MVT::i32), // PTR
806 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), MVT::i32);
848 CC = DAG.getCondCode(ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32));
852 (CompareVT == VT || VT == MVT::i32)) {
892 CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
918 if (CompareVT == MVT::f32) {
921 } else if (CompareVT == MVT::i32) {
944 DAG.getConstant(0, MVT::i32),
973 DAG.getConstant(SRLPad, MVT::i32));
1017 Ptr, DAG.getConstant(2, MVT::i32)));
1053 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1054 DAG.getConstant(PtrIncr, MVT::i32));
1056 Value, DAG.getConstant(i, MVT::i32));
1058 Stores[i] = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1060 DAG.getTargetConstant(Channel, MVT::i32));
1062 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Stores, NumElemVT);
1064 if (ValueVT == MVT::i8) {
1065 Value = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Value);
1067 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other, Chain, Value, Ptr,
1068 DAG.getTargetConstant(0, MVT::i32)); // Channel
1138 DAG.getConstant(4 * i + ConstantBlock * 16, MVT::i32));
1139 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1141 EVT NewVT = MVT::v4i32;
1150 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32,
1151 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
1153 AMDGPUAS::CONSTANT_BUFFER_0, MVT::i32)
1158 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result,
1159 DAG.getConstant(0, MVT::i32));
1178 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1180 DAG.getConstant(VT.getSizeInBits() - MemVT.getSizeInBits(), MVT::i32);
1216 Ptr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
1217 DAG.getConstant(PtrIncr, MVT::i32));
1220 DAG.getTargetConstant(Channel, MVT::i32),
1231 DAG.getTargetConstant(0, MVT::i32), // Channel
1268 DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
1278 if (!VT.isVector()) return MVT::i32;
1298 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1301 NewBldVec[i] = DAG.getUNDEF(MVT::f32);
1362 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1370 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], MVT::i32);
1389 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1408 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS
1409 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True
1418 DAG.getConstant(-1, MVT::i32), // True
1419 DAG.getConstant(0, MVT::i32), // Flase
