Lines Matching refs:SELECT_CC
65 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
95 setTargetDAGCombine(ISD::SELECT_CC);
488 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
839 // select_cc f32, f32, -1, 0, cc_any
840 // select_cc f32, f32, 1.0f, 0.0f, cc_any
841 // select_cc i32, i32, -1, 0, cc_any
854 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
861 // select_cc f32, 0.0, f32, f32, cc_any
862 // select_cc f32, 0.0, i32, i32, cc_any
863 // select_cc i32, 0, f32, f32, cc_any
864 // select_cc i32, 0, i32, i32, cc_any
900 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
915 // this SELECT_CC, so we must lower it.
929 // Lower this unsupported SELECT_CC into a combination of two supported
930 // SELECT_CC operations.
931 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC);
933 return DAG.getNode(ISD::SELECT_CC, DL, VT,
940 return DAG.getNode(ISD::SELECT_CC,
1396 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1397 // (i32 select_cc f32, f32, -1, 0 cc)
1407 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1415 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),
1499 case ISD::SELECT_CC: {
1506 if (LHS.getOpcode() != ISD::SELECT_CC) {
