Lines Matching refs:v4f32
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
41 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
43 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
45 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
47 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
552 MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
646 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs, 19);
1149 // non constant ptr cant be folded, keeps it as a v4f32 load
