Lines Matching refs:AMDGPU
51 #include "AMDGPU.h"
138 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
140 .addReg(AMDGPU::EXEC);
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
157 .addReg(AMDGPU::EXEC);
160 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
166 .addReg(AMDGPU::VGPR0)
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0);
172 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
181 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
184 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
185 .addReg(AMDGPU::EXEC)
200 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
204 .addReg(AMDGPU::EXEC)
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
220 .addReg(AMDGPU::EXEC)
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
249 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
261 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
262 .addReg(AMDGPU::EXEC)
265 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
267 .addReg(AMDGPU::EXEC);
278 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
279 .addReg(AMDGPU::EXEC)
304 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
320 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
321 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
328 assert(AMDGPU::SReg_64RegClass.contains(Save));
329 assert(AMDGPU::VReg_32RegClass.contains(Idx));
332 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
333 .addReg(AMDGPU::EXEC);
336 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
340 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
341 .addReg(AMDGPU::VCC);
344 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
345 .addReg(AMDGPU::M0)
349 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
350 .addReg(AMDGPU::VCC);
356 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
357 .addReg(AMDGPU::EXEC)
358 .addReg(AMDGPU::VCC);
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
363 .addReg(AMDGPU::EXEC);
366 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
382 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
383 .addReg(TRI->getSubReg(Vec, AMDGPU::sub0) + Off)
384 .addReg(AMDGPU::M0, RegState::Implicit)
400 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
403 .addReg(AMDGPU::M0, RegState::Implicit)
429 case AMDGPU::SI_IF:
434 case AMDGPU::SI_ELSE:
438 case AMDGPU::SI_BREAK:
442 case AMDGPU::SI_IF_BREAK:
446 case AMDGPU::SI_ELSE_BREAK:
450 case AMDGPU::SI_LOOP:
455 case AMDGPU::SI_END_CF:
463 case AMDGPU::SI_KILL:
471 case AMDGPU::S_BRANCH:
475 case AMDGPU::SI_INDIRECT_SRC:
479 case AMDGPU::SI_INDIRECT_DST_V2:
480 case AMDGPU::SI_INDIRECT_DST_V4:
481 case AMDGPU::SI_INDIRECT_DST_V8:
482 case AMDGPU::SI_INDIRECT_DST_V16:
486 case AMDGPU::DS_READ_B32:
489 case AMDGPU::DS_WRITE_B32:
493 case AMDGPU::V_INTERP_P1_F32:
494 case AMDGPU::V_INTERP_P2_F32:
495 case AMDGPU::V_INTERP_MOV_F32:
507 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
508 AMDGPU::M0).addImm(0xffffffff);
513 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
514 AMDGPU::EXEC).addReg(AMDGPU::EXEC);
