Lines Matching refs:VCC
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
179 unsigned Vcc = MI.getOperand(1).getReg();
182 .addReg(Vcc);
231 unsigned Vcc = MI.getOperand(1).getReg();
235 .addReg(Vcc)
304 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
335 // Read the next variant into VCC (lower 32 bits) <- also loop target
336 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
339 // Move index from VCC into M0
341 .addReg(AMDGPU::VCC);
344 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
348 // Update EXEC, save the original EXEC value to VCC
349 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
350 .addReg(AMDGPU::VCC);
358 .addReg(AMDGPU::VCC);
