Lines Matching refs:RegKind
86 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
92 unsigned RegKind : 8;
150 static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
155 Op->Mem.RegKind = RegKind;
176 bool isReg(RegisterKind RegKind) const {
177 return Kind == KindReg && Reg.Kind == RegKind;
206 bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
208 Mem.RegKind == RegKind &&
212 bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
213 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
215 bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
216 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
218 bool isMemDisp12Len8(RegisterKind RegKind) const {
219 return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
319 const unsigned *Regs, RegisterKind RegKind);
323 const unsigned *Regs, RegisterKind RegKind,
506 // Regs maps asm register numbers to LLVM register numbers and RegKind
511 RegisterKind RegKind) {
526 if (parseRegister(Reg, RegGR, Regs, RegKind))
542 if (parseRegister(Reg, RegGR, Regs, RegKind))
559 const unsigned *Regs, RegisterKind RegKind,
565 if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
588 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
