Lines Matching refs:STD
313 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
407 static std::pair<unsigned, const TargetRegisterClass *>
408 parseRegisterNumber(const std::string &Constraint,
412 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
415 return std::make_pair(Map[Index], RC);
417 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
420 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
421 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
429 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
431 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
432 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
436 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
438 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
439 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
443 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
445 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
446 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
479 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
480 std::vector<SDValue> &Ops,
724 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
744 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
2304 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2306 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
