Lines Matching full:opcode
37 // each having the opcode given by NewOpcode.
296 // If Opcode is a move that has a conditional variant, return that variant,
298 static unsigned getConditionalMove(unsigned Opcode) {
299 switch (Opcode) {
307 unsigned Opcode = MI->getOpcode();
309 getConditionalMove(Opcode))
339 unsigned Opcode = MI->getOpcode();
341 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
367 unsigned Opcode;
369 Opcode = SystemZ::LR;
371 Opcode = SystemZ::LGR;
373 Opcode = SystemZ::LER;
375 Opcode = SystemZ::LDR;
377 Opcode = SystemZ::LXR;
381 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
439 static LogicOp interpretAndImmediate(unsigned Opcode) {
440 switch (Opcode) {
477 unsigned Opcode = MI->getOpcode();
485 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
502 if (LogicOp And = interpretAndImmediate(Opcode)) {
553 unsigned Opcode = MI->getOpcode();
554 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
555 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
556 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
606 int MemOpcode = SystemZ::getMemOpcode(Opcode);
706 llvm_unreachable("Unrecognized branch opcode");
737 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
739 const MCInstrDesc &MCID = get(Opcode);
743 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
749 return Opcode;
753 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
757 // Check whether Opcode allows signed 20-bit displacements.
759 return Opcode;
764 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
765 switch (Opcode) {
822 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
824 switch (Opcode) {
842 unsigned Opcode;
844 Opcode = SystemZ::LGHI;
846 Opcode = SystemZ::LLILL;
848 Opcode = SystemZ::LLILH;
852 Opcode = SystemZ::LGFI;
854 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
