Lines Matching refs:SystemZ
1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
32 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
51 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
52 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
118 if (MI->getOpcode() != SystemZ::MVC ||
172 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
271 "SystemZ branch conditions have one component!");
276 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
284 BuildMI(&MBB, DL, get(SystemZ::BRC))
290 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
300 case SystemZ::LR: return SystemZ::LOCR;
301 case SystemZ::LGR: return SystemZ::LOCGR;
345 .addReg(SystemZ::CC, RegState::Implicit);;
358 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
359 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
360 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
361 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
362 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
368 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
369 Opcode = SystemZ::LR;
370 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
371 Opcode = SystemZ::LGR;
372 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
373 Opcode = SystemZ::LER;
374 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
375 Opcode = SystemZ::LDR;
376 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
377 Opcode = SystemZ::LXR;
441 case SystemZ::NILL32: return LogicOp(32, 0, 16);
442 case SystemZ::NILH32: return LogicOp(32, 16, 16);
443 case SystemZ::NILL: return LogicOp(64, 0, 16);
444 case SystemZ::NILH: return LogicOp(64, 16, 16);
445 case SystemZ::NIHL: return LogicOp(64, 32, 16);
446 case SystemZ::NIHH: return LogicOp(64, 48, 16);
447 case SystemZ::NILF32: return LogicOp(32, 0, 32);
448 case SystemZ::NILF: return LogicOp(64, 0, 32);
449 case SystemZ::NIHF: return LogicOp(64, 32, 32);
485 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
505 NewOpcode = SystemZ::RISBG;
507 NewOpcode = SystemZ::RISBLG32;
518 if (NewOpcode == SystemZ::RISBLG32) {
554 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
555 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
556 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
560 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
568 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
589 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
596 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
606 int MemOpcode = SystemZ::getMemOpcode(Opcode);
638 case SystemZ::L128:
639 splitMove(MI, SystemZ::LG);
642 case SystemZ::ST128:
643 splitMove(MI, SystemZ::STG);
646 case SystemZ::LX:
647 splitMove(MI, SystemZ::LD);
650 case SystemZ::STX:
651 splitMove(MI, SystemZ::STD);
654 case SystemZ::ADJDYNALLOC:
675 case SystemZ::BR:
676 case SystemZ::J:
677 case SystemZ::JG:
678 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
679 SystemZ::CCMASK_ANY, &MI->getOperand(0));
681 case SystemZ::BRC:
682 case SystemZ::BRCL:
687 case SystemZ::BRCT:
688 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
689 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
691 case SystemZ::BRCTG:
692 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
693 SystemZ::CCMASK_CMP_NE, &MI->getOperand(2));
695 case SystemZ::CIJ:
696 case SystemZ::CRJ:
697 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
700 case SystemZ::CGIJ:
701 case SystemZ::CGRJ:
702 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
713 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
714 LoadOpcode = SystemZ::L;
715 StoreOpcode = SystemZ::ST32;
716 } else if (RC == &SystemZ::GR64BitRegClass ||
717 RC == &SystemZ::ADDR64BitRegClass) {
718 LoadOpcode = SystemZ::LG;
719 StoreOpcode = SystemZ::STG;
720 } else if (RC == &SystemZ::GR128BitRegClass ||
721 RC == &SystemZ::ADDR128BitRegClass) {
722 LoadOpcode = SystemZ::L128;
723 StoreOpcode = SystemZ::ST128;
724 } else if (RC == &SystemZ::FP32BitRegClass) {
725 LoadOpcode = SystemZ::LE;
726 StoreOpcode = SystemZ::STE;
727 } else if (RC == &SystemZ::FP64BitRegClass) {
728 LoadOpcode = SystemZ::LD;
729 StoreOpcode = SystemZ::STD;
730 } else if (RC == &SystemZ::FP128BitRegClass) {
731 LoadOpcode = SystemZ::LX;
732 StoreOpcode = SystemZ::STX;
743 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
753 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
766 case SystemZ::L: return SystemZ::LT;
767 case SystemZ::LY: return SystemZ::LT;
768 case SystemZ::LG: return SystemZ::LTG;
769 case SystemZ::LGF: return SystemZ::LTGF;
770 case SystemZ::LR: return SystemZ::LTR;
771 case SystemZ::LGFR: return SystemZ::LTGFR;
772 case SystemZ::LGR: return SystemZ::LTGR;
773 case SystemZ::LER: return SystemZ::LTEBR;
774 case SystemZ::LDR: return SystemZ::LTDBR;
775 case SystemZ::LXR: return SystemZ::LTXBR;
825 case SystemZ::CR:
826 return SystemZ::CRJ;
827 case SystemZ::CGR:
828 return SystemZ::CGRJ;
829 case SystemZ::CHI:
830 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
831 case SystemZ::CGHI:
832 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
844 Opcode = SystemZ::LGHI;
845 else if (SystemZ::isImmLL(Value))
846 Opcode = SystemZ::LLILL;
847 else if (SystemZ::isImmLH(Value)) {
848 Opcode = SystemZ::LLILH;
852 Opcode = SystemZ::LGFI;
