Lines Matching refs:MCInst
22 #include "llvm/MC/MCInst.h"
71 static bool translateInstruction(MCInst &target,
115 X86GenericDisassembler::getInstruction(MCInst &instr,
154 /// register, and appends it as an operand to an MCInst.
156 /// @param mcInst - The MCInst to append to.
158 static void translateRegister(MCInst &mcInst, Reg reg) {
167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
171 /// immediate Value in the MCInst.
184 /// an MCExpr and that is added as an operand to the MCInst. If getOpInfo()
188 /// if it adds an operand to the MCInst and false otherwise.
191 uint64_t Width, MCInst &MI,
210 /// translateImmediate - Appends an immediate operand to an MCInst.
212 /// @param mcInst - The MCInst to append to.
216 static void translateImmediate(MCInst &mcInst, uint64_t immediate,
250 uint32_t Opcode = mcInst.getOpcode();
284 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
287 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
290 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
321 mcInst, Dis))
322 mcInst.addOperand(MCOperand::CreateImm(immediate));
326 /// ModR/M byte to its LLVM equivalent and appends it to an MCInst.
327 /// @param mcInst - The MCInst to append to.
331 static bool translateRMRegister(MCInst &mcInst,
353 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
363 /// operand in LLVM's format, and appends it to an MCInst.
365 /// @param mcInst - The MCInst to append to.
369 static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
371 // Addresses in an MCInst are represented as five operands:
412 uint32_t Opcode = mcInst.getOpcode();
534 mcInst.addOperand(baseReg);
535 mcInst.addOperand(scaleAmount);
536 mcInst.addOperand(indexReg);
539 insn.displacementSize, mcInst, Dis))
540 mcInst.addOperand(displacement);
541 mcInst.addOperand(segmentReg);
546 /// byte of an instruction to LLVM form, and appends it to an MCInst.
548 /// @param mcInst - The MCInst to append to.
553 static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
575 return translateRMRegister(mcInst, insn);
595 return translateRMMemory(mcInst, insn, Dis);
600 /// LLVM form, and appends it to an MCInst.
602 /// @param mcInst - The MCInst to append to.
605 static bool translateFPRegister(MCInst &mcInst,
612 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
618 /// to LLVM's format and appends it to an MCInst.
620 /// @param mcInst - The MCInst to append to.
624 static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
632 translateRegister(mcInst, insn.reg);
635 return translateRM(mcInst, operand, insn, Dis);
650 translateImmediate(mcInst,
660 translateRegister(mcInst, insn.opcodeRegister);
663 return translateFPRegister(mcInst, insn.opcodeModifier);
665 translateRegister(mcInst, insn.opcodeRegister);
668 translateRegister(mcInst, insn.vvvv);
671 return translateOperand(mcInst, insn.operands[operand.type - TYPE_DUP0],
677 /// operands to an MCInst.
679 /// @param mcInst - The MCInst to populate with the instruction's data.
682 static bool translateInstruction(MCInst &mcInst,
690 mcInst.setOpcode(insn.instructionID);
695 if(mcInst.getOpcode() == X86::REP_PREFIX)
696 mcInst.setOpcode(X86::XRELEASE_PREFIX);
697 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
698 mcInst.setOpcode(X86::XACQUIRE_PREFIX);
707 if (translateOperand(mcInst, insn.operands[index], insn, Dis)) {
