Lines Matching defs:BaseReg
221 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
224 if ((BaseReg.getReg() != 0 &&
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
236 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
239 if ((BaseReg.getReg() != 0 &&
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
251 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
254 if ((BaseReg.getReg() != 0 &&
255 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
374 unsigned BaseReg = Base.getReg();
378 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
403 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
406 // If no BaseReg, issue a RIP relative instruction only if the MCE can
418 (!is64BitMode() || BaseReg != 0)) {
420 if (BaseReg == 0) { // [disp32] in X86-32 mode
468 if (BaseReg == 0) {
501 if (BaseReg == 0) {
