Lines Matching full:opcode
527 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
539 // VEX_R: opcode externsion equivalent to REX.R in
562 // VEX_W: opcode specific (use like REX.W, or used for
563 // opcode extension, or ignored, depending on the opcode byte)
572 // 0b00001: implied 0F leading opcode
573 // 0b00010: implied 0F 38 leading opcode bytes
574 // 0b00011: implied 0F 3A leading opcode bytes
593 // VEX_PP: opcode extension providing equivalent
615 // Encode the operand size opcode prefix as needed.
888 // Emit segment override opcode prefix as needed.
892 // VEX opcode prefix can have 2 or 3 bytes
916 // EVEX opcode prefix can have 4 bytes
1039 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
1070 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
1079 // Emit the lock opcode prefix as needed.
1083 // Emit segment override opcode prefix as needed.
1086 // Emit the repeat opcode prefix as needed.
1090 // Emit the address size opcode prefix as needed.
1109 // Emit the operand size opcode prefix as needed.
1118 case X86II::TB: // Two-byte opcode prefix
1162 // 0x0F escape code must be emitted just before the opcode.
1189 unsigned Opcode = MI.getOpcode();
1190 const MCInstrDesc &Desc = MCII.get(Opcode);
1217 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode);
