Lines Matching full:instruction
64 virtual bool TargetSelectInstruction(const Instruction *I);
67 /// vreg is being provided by the specified load instruction. If possible,
68 /// try to fold the load as an operand to the instruction, returning true if
93 bool X86SelectLoad(const Instruction *I);
95 bool X86SelectStore(const Instruction *I);
97 bool X86SelectRet(const Instruction *I);
99 bool X86SelectCmp(const Instruction *I);
101 bool X86SelectZExt(const Instruction *I);
103 bool X86SelectBranch(const Instruction *I);
105 bool X86SelectShift(const Instruction *I);
107 bool X86SelectDivRem(const Instruction *I);
109 bool X86SelectSelect(const Instruction *I);
111 bool X86SelectTrunc(const Instruction *I);
113 bool X86SelectFPExt(const Instruction *I);
114 bool X86SelectFPTrunc(const Instruction *I);
117 bool X86SelectCall(const Instruction *I);
119 bool DoSelectCall(const Instruction *I, const char *MemIntName);
167 // We only handle legal types. For example, on x86-32 the instruction
176 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
181 // Get opcode and regclass of the output for the given load instruction.
233 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
240 // Get opcode and regclass of the output for the given store instruction.
332 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
351 unsigned Opcode = Instruction::UserOp1;
352 if (const Instruction *I = dyn_cast<Instruction>(V)) {
368 // Fast instruction selection doesn't support the special
374 case Instruction::BitCast:
378 case Instruction::IntToPtr:
384 case Instruction::PtrToInt:
390 case Instruction::Alloca: {
403 case Instruction::Add: {
416 case Instruction::GetElementPtr: {
445 (!isa<Instruction>(Op) ||
446 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
611 unsigned Opcode = Instruction::UserOp1;
612 if (const Instruction *I = dyn_cast<Instruction>(V)) {
622 case Instruction::BitCast:
626 case Instruction::IntToPtr:
632 case Instruction::PtrToInt:
696 bool X86FastISel::X86SelectStore(const Instruction *I) {
719 bool X86FastISel::X86SelectRet(const Instruction *I) {
821 // Add register to return instruction.
850 bool X86FastISel::X86SelectLoad(const Instruction *I) {
941 bool X86FastISel::X86SelectCmp(const Instruction *I) {
1019 bool X86FastISel::X86SelectZExt(const Instruction *I) {
1070 bool X86FastISel::X86SelectBranch(const Instruction *I) {
1199 bool X86FastISel::X86SelectShift(const Instruction *I) {
1206 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1207 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1208 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1215 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1216 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1217 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1224 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1225 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1226 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1233 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1234 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1235 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1254 // The shift instruction uses X86::CL. If we defined a super-register
1268 bool X86FastISel::X86SelectDivRem(const Instruction *I) {
1274 // For the X86 DIV/IDIV instruction, in most cases the dividend
1277 // For most data types, to set up the instruction, the dividend is
1347 case Instruction::SDiv: OpIndex = 0; break;
1348 case Instruction::SRem: OpIndex = 1; break;
1349 case Instruction::UDiv: OpIndex = 2; break;
1350 case Instruction::URem: OpIndex = 3; break;
1393 // Generate the DIV/IDIV instruction.
1398 // instead to prevent AH references in a REX instruction.
1405 if ((I->getOpcode() == Instruction::SRem ||
1406 I->getOpcode() == Instruction::URem) &&
1432 bool X86FastISel::X86SelectSelect(const Instruction *I) {
1437 // We only use cmov here, if we don't have a cmov instruction bail.
1471 bool X86FastISel::X86SelectFPExt(const Instruction *I) {
1491 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
1511 bool X86FastISel::X86SelectTrunc(const Instruction *I) {
1677 // Replace "add with overflow" intrinsics with an "add" instruction followed
1678 // by a seto/setc instruction.
1785 // use is a bitcast (which isn't turned into an instruction).
1794 bool X86FastISel::X86SelectCall(const Instruction *I) {
1830 bool X86FastISel::DoSelectCall(const Instruction *I, const char *MemIntName) {
1929 // instruction. This is safe because it is common to all fastisel supported
2261 X86FastISel::TargetSelectInstruction(const Instruction *I) {
2264 case Instruction::Load:
2266 case Instruction::Store:
2268 case Instruction::Ret:
2270 case Instruction::ICmp:
2271 case Instruction::FCmp:
2273 case Instruction::ZExt:
2275 case Instruction::Br:
2277 case Instruction::Call:
2279 case Instruction::LShr:
2280 case Instruction::AShr:
2281 case Instruction::Shl:
2283 case Instruction::SDiv:
2284 case Instruction::UDiv:
2285 case Instruction::SRem:
2286 case Instruction::URem:
2288 case Instruction::Select:
2290 case Instruction::Trunc:
2292 case Instruction::FPExt:
2294 case Instruction::FPTrunc:
2296 Instruction::IntToPtr: // Deliberate fall-through.
2297 case Instruction::PtrToInt: {
2323 // Get opcode and regclass of the output for the given load instruction.
