Lines Matching refs:ISD
87 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
334 /// ISD::SIGN_EXTEND).
335 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT,
755 SmallVector<ISD::OutputArg, 4> Outs;
806 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
807 ISD::SIGN_EXTEND;
1059 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND,
1863 SmallVector<ISD::OutputArg, 4> Outs;
1889 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1902 ISD::ArgFlagsTy Flags;
1955 ArgReg = FastEmit_ri(ArgVT, ArgVT, ISD::AND, ArgReg,
2011 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
2020 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
2029 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
2032 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
2035 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
2044 ISD::BITCAST, Arg, /*TODO: Kill=*/false);
2072 ISD::ArgFlagsTy Flags = ArgFlags[VA.getValNo()];
2184 SmallVector<ISD::InputArg, 32> Ins;
2192 ISD::InputArg MyFlags;
