Lines Matching refs:OpEntry
1354 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1364 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1366 if (OpEntry.OpSignExtend) {
1367 if (OpEntry.IsOpSigned)
1369 TII.get(OpEntry.OpSignExtend));
1395 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1407 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
1425 .addReg(OpEntry.DivRemResultReg);
